Search Results - "Ferriss, M."

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  1. 1

    A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback by Dalton, D., Kwet Chai, Evans, E., Ferriss, M., Hitchcox, D., Murray, P., Selvanayagam, S., Shepherd, P., DeVito, L.

    Published in IEEE journal of solid-state circuits (01-12-2005)
    “…A continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described. The circuit automatically detects a change in…”
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    Journal Article
  2. 2

    A 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW by Sadhu, B., Valdes-Garcia, A., Plouchart, J.-O, Ainspan, H., Gupta, A. K., Ferriss, M., Yeck, M., Sanduleanu, M., Gu, X., Baks, C., Liu, D., Friedman, D.

    “…A low power, small form-factor, 60-GHz radio with beam switching capability is presented. The 3mm×3mm radio IC in 32nm SOI CMOS includes the TX and RX RF front…”
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    Conference Proceeding Journal Article
  3. 3

    An Integral Path Self-Calibration Scheme for a Dual-Loop PLL by Ferriss, M., Plouchart, J., Natarajan, A., Rylyakov, A., Parker, B., Tierno, J., Babakhani, A., Yaldiz, S., Valdes-Garcia, A., Sadhu, B., Friedman, D.

    Published in IEEE journal of solid-state circuits (01-04-2013)
    “…An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in…”
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    Journal Article Conference Proceeding
  4. 4

    Symplectic No-core Shell-model Approach to Intermediate-mass Nuclei by Tobin, G. K, Ferriss, M. C, Launey, K. D, Dytrych, T, Draayer, J. P, Dreyfuss, A. C, Bahri, C

    Published 09-11-2013
    “…We present a microscopic description of nuclei in an intermediate-mass region, including the proximity to the proton drip line, based on a no-core shell model…”
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    Journal Article
  5. 5

    A 14 mW Fractional-@@iN@ PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme by Ferriss, M A, Flynn, M P

    Published in IEEE journal of solid-state circuits (01-11-2008)
    “…In this work an all-digital phase detector for a fractional-N PLL is proposed and demonstrated. The phase detector consists of a single flip-flop, which acts…”
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    Journal Article
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    A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS by Plouchart, J.-O., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., Friedman, D., Ferriss, M., Natarajan, A. S., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B. D., Beakes, M., Babakhani, A.

    “…A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power…”
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    Journal Article
  8. 8

    GP budget holding in the United Kingdom: learning from American HMOs by Weiner, J P, Ferriss, D M

    Published in Health policy (Amsterdam) (01-12-1990)
    “…A key component of the 1989 British National Health Service White Paper, 'Working for Patients', is the so-called budget holding plan for general…”
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    Journal Article
  9. 9

    Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion by Sun, S., Wang, F., Yaldiz, S., Li, X., Pileggi, L., Natarajan, A., Ferriss, M., Plouchart, J., Sadhu, B., Parker, B., Valdes-Garcia, A., Sanduleanu, M., Tierno, J., Friedman, D.

    “…On-chip analog self-healing requires low-cost sensors to accurately measure various performance metrics. In this paper we propose a novel approach of indirect…”
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    Conference Proceeding
  10. 10

    Indirect phase noise sensing for self-healing voltage controlled oscillators by Yaldiz, S., Calayir, V., Li, X., Pileggi, L., Natarajan, A. S., Ferriss, M. A., Tierno, J.

    “…The push for higher performance analog/RF circuits in scaled CMOS necessitates self-healing via post-manufacturing tuning. A major challenge with self-healing…”
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    Conference Proceeding
  11. 11

    A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS by Ghahramani, M. M., Ferriss, M. A., Flynn, M. P.

    “…A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables…”
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    Conference Proceeding
  12. 12

    A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS by Plouchart, J.-O, Ferriss, M., Natarajan, A., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B., Beakes, M., Babakani, A., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., Friedman, D.

    “…A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption…”
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    Conference Proceeding
  13. 13

    A fractional-N PLL modulator with flexible direct digital phase modulation by Ferriss, M., Lin, D.T., Flynn, M.P.

    “…A 2.6 GHz fractional-N synthesizer with a flexible digital modulation scheme is presented. The PLL output is modulated by adding a digital signal directly to…”
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    Conference Proceeding
  14. 14

    A 21.8-27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier by Sadhu, B., Ferriss, M. A., Plouchart, J-O, Natarajan, A. S., Rylyakov, A. V., Valdes-Garcia, A., Parker, B. D., Reynolds, S., Babakhani, A., Yaldiz, S., Pileggi, L., Harjani, R., Tierno, J., Friedman, D.

    “…This paper describes a new approach to low phase noise LC VCO design based on transconductance linearization of the active devices. A prototype 25GHz VCO based…”
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    Conference Proceeding
  15. 15

    A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme by Ferriss, M.A., Flynn, M.P.

    Published in IEEE journal of solid-state circuits (01-11-2008)
    “…In this work an all-digital phase detector for a fractional-N PLL is proposed and demonstrated. The phase detector consists of a single flip-flop, which acts…”
    Get full text
    Journal Article
  16. 16

    A 12.5 Mb/s to 2.7 Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback by Dalton, D., Chai, K., Evans, E., Ferriss, M., Hitchcox, D., Murray, P., Selvanayagam, S., Shepherd, P., DeVito, L.

    “…A continuous-rate CDR (clock and data recovery) circuit is presented that operates from 12.5 Mb/s to 2.7 Gb/s. The circuit automatically detects a change in…”
    Get full text
    Conference Proceeding
  17. 17

    An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS by Ferriss, M., Plouchart, J., Natarajan, A., Rylyakov, A., Parker, B., Babakhani, A., Yaldiz, S., Sadhu, B., Valdes-Garcia, A., Tierno, J., Friedman, D.

    Published in 2012 Symposium on VLSI Circuits (VLSIC) (01-06-2012)
    “…A bandwidth self-calibration scheme is introduced as part of a 20.1GHz to 26.7GHz, low noise PLL in 32nm CMOS SOI. A dual-loop architecture in combination with…”
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    Conference Proceeding
  18. 18

    Cancer in Obese Women: Potential Protective Impact of Bariatric Surgery by McCawley, Gwyneth M., BA, Ferriss, J. Stuart, MD, Geffel, Dyanna, BS, Northup, C. Joe, MD, FACS, Modesitt, Susan C., MD, FACS

    “…Background The use of bariatric surgery has been increasing over the last several years in response to the obesity epidemic, and the objective of this study…”
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    Journal Article
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