A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS

This paper describes a 0.5-16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provide...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 50; no. 8; pp. 1932 - 1944
Main Authors:	Frans, Yohan, Carey, Declan, Erett, Marc, Amir-Aslanzadeh, Hesam, Fang, Wayne Y., Turker, Didem, Jose, Anup P., Bekele, Adebabay, Im, Jay, Upadhyaya, Parag, Wu, Zhaoyin Daniel, Hsieh, Kenny C. H., Savoj, Jafar, Chang, Ken
Format:	Journal Article
Language:	English
Published:	New York IEEE 01-08-2015 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	adaptive Adjustable Bandwidth Channels Circuits Clocks CMOS Decision feedback equalizers FGPA Field programmable gate arrays Gain Gain control Jitter Receivers serdes serial link Transceiver Transceivers wireline
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Summary:	This paper describes a 0.5-16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provides reliable operation across all data rates. Low-latency digital CDR ensures high tracking bandwidth while still providing flexibility to support multiple protocols. The transceiver uses ring-oscillator with programmable main and cross-coupled inverter drive-strengths to wide range of operating frequency for low data-rate operation. A wide range low jitter LC-PLL utilizes feedback divider with synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The clock distribution uses quadrature-error correction circuit to improve phase interpolator linearity. The transceiver achieves BER <;10 -15 over a 28 dB loss backplane at 16.3 Gb/s and over legacy channels with 10 G-KR characteristics at 10.3125 Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8 Gb/s and PCIe Gen4 at 16 Gb/s in both common-clock and spread-spectrum modes.
Bibliography:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2015.2413849