Search Results - "Fahmy, A.H."
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1
Trajectory control and image encryption using affine transformation of lorenz system
Published in Egyptian informatics journal (01-07-2021)“…This paper presents a generalization of chaotic systems using two-dimensional affine transformations with six introduced parameters to achieve scaling,…”
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2
Protection Against Fusarium Head Blight: Important Defense Mechanisms Studied in Three Regenerated Egyptian Wheat Cultivars
Published in Journal of stress physiology & biochemistry (01-01-2016)“…Fusarium graminearum is one of the major global pathogens of cereals and is considered the main causal agent of Fusarium head blight (FHB) disease in wheat. F…”
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3
Finite Precision Logistic Map between Computational Efficiency and Accuracy with Encryption Applications
Published in Complexity (New York, N.Y.) (01-01-2017)“…Chaotic systems appear in many applications such as pseudo-random number generation, text encryption, and secure image transfer. Numerical solutions of these…”
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4
Design of Positive, Negative, and Alternating Sign Generalized Logistic Maps
Published in Discrete Dynamics in Nature and Society (01-01-2015)“…The discrete logistic map is one of the most famous discrete chaotic maps which has widely spread applications. This paper investigates a set of four…”
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5
Fair memory access scheduling algorithms for multicore processors
Published in International journal of parallel, emergent and distributed systems (04-07-2015)“…In recent processors multicore and multithreaded architectures are widely used. This increases the number of contexts running in parallel. Contexts are…”
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6
Two Extended Programmable BCH Soft Decoders Using Least Reliable Bits Reprocessing
Published in Circuits, systems, and signal processing (01-05-2014)“…This paper proposes two Bose–Chaudhuri–Hocquenghem (BCH) soft decoders suitable for high-rate codes with medium to large word length. The proposed decoders…”
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7
Two programmable BCH soft decoders for high rate codes with large word length
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01-05-2013)“…In this paper, two BCH soft decoders are proposed suitable for high rate codes with medium to large word length. The proposed decoders provide a programmable…”
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Conference Proceeding -
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Low energy pipelined Dual Base (decimal/binary) Multiplier, DBM, design
Published in Microelectronics (01-07-2017)“…Combined binary/decimal arithmetic is optimal in supporting binary and decimal high speed and low power applications. A low energy clock-gated pipelined dual…”
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9
Propagation of acoustic surface waves in multilayers: A matrix description
Published in Applied physics letters (15-05-1973)“…A matrix formalism is outlined for studying surface wave propagation in layered structures utilizing materials of arbitrary anisotropy, piezoelectricity, and…”
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10
Single-Readout High-Density Memristor Crossbar
Published in Scientific reports (07-01-2016)“…High-density memristor-crossbar architecture is a very promising technology for future computing systems. The simplicity of the gateless-crossbar structure is…”
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11
Software and Hardware Implementation Sensitivity of Chaotic Systems and Impact on Encryption Applications
Published in Circuits, systems, and signal processing (01-11-2020)“…This paper discusses the implementation sensitivity of chaotic systems added to their widely discussed sensitivities to initial conditions and parameter…”
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12
Memristor Multiport Readout: A Closed-Form Solution for Sneak Paths
Published in IEEE transactions on nanotechnology (01-03-2014)“…In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The…”
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13
Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit
Published in IEEE transactions on computers (01-02-2017)“…In this work we present a new 64-bit floating point Fused Multiply Add (FMA) unit that can perform both binary and decimal addition, multiplication, and…”
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14
NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA
Published in Integration (Amsterdam) (01-09-2018)“…Due to the ability of Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) to add more flexibility over runtime phase,…”
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15
Enhanced Model of Conductive Filament-Based Memristor via Including Trapezoidal Electron Tunneling Barrier Effect
Published in IEEE transactions on nanotechnology (01-05-2016)“…Memristors exhibit very promising features such as nonvolatility and small area. Several types of memristors have been developed in the last decade using…”
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16
Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources
Published in Integration (Amsterdam) (01-09-2018)“…FPGA has become a favorable platform for Systems-on-Chip (SoC). As SoC gets larger, a Network-on-Chip (NoC) emerges as a promising solution for communication…”
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17
Compensated Readout for High-Density MOS-Gated Memristor Crossbar Array
Published in IEEE transactions on nanotechnology (01-01-2015)“…Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory…”
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18
A simplified radix-4 successive cancellation decoder with partial sum lookahead
Published in International journal of electronics and communications (01-11-2018)“…Polar codes recently received high attention by researchers as proven to approach channel capacity at higher codeword length. However, the decoding latency…”
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19
Cotton (Gossypium barbadense L.) yield and fiber properties as affected by plant growth retardants and plant density
Published in Journal of crop improvement (16-04-2008)“…Chemicals may be used to reduce plant size in cotton (Gossypium barbadense L.), which can increase cotton yield by allowing an increased number of plants per…”
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20
Design Framework to Overcome Aging Degradation of the 16 nm VLSI Technology Circuits
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-05-2014)“…Intensive scaling for VLSI circuits is a key factor for gaining outstanding performance. However, this scaling has huge negative impact on the circuit…”
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