Search Results - "European Test Symposium (ETS'05)"

Foreword

“…These proceedings contain all the papers presented at the symposium that have been selected from the set of papers submitted to the 'formal' category. Indeed,…”
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Test control for secure scan designs by Hely, D., Bancel, F., Flottes, M.L., Rouzeyre, B.

“…Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in…”
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Defective behaviours of resistive opens in interconnect lines by Arumi, D., Rodriguez-Montane, R., Figueras, J.

“…Defective interconnect lines affected by open defects have been intentionally designed and introduced on a CMOS digital test circuit. A simple bus structure…”
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Multiple errors produced by single upsets in FPGA configuration memory: a possible solution by Sonza Reorda, M., Sterpone, L., Violante, M.

“…The very high integration levels reached by SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence rate of single event upsets (SEUs) in…”
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Test scheduling for modular SOCs in an abort-on-fail environment by Ingelsson, U., Goel, S.K., Larsson, E., Marinissen, E.J.

“…Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as…”
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A unified fault model and test generation procedure for interconnect opens and bridges by Chen, G., Reddy, S., Pomeranz, I., Rajski, J., Engelke, P., Becker, B.

“…A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel…”
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Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels by Kinsman, A.B., Nicolici, N.

“…In this paper we first observe that the required amount of compressed test data transferred from the tester to the embedded cores in a system-on-a-chip (SOC)…”
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Automatic March tests generation for static and dynamic faults in SRAMs by Benso, A., Bosio, A., Di Carlo, S., Di Natale, G., Prinetto, P.

“…New memory production modern technologies introduce new classes of faults usually referred to as dynamic memory faults. Although some hand-made March tests to…”
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A new SoC test architecture with RF/wireless connectivity by Zhao, D., Upadhyaya, S., Margala, M.

“…When moving into the billion-transistor era, the direct or bus interconnects in conventional SoC test control models are rather restricted in not only system…”
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Logic circuit testing for transient faults by Krishnaswamy, S., Markov, I.L., Hayes, J.P.

“…Transient faults are becoming an increasingly serious concern for logic circuits. They can be caused by thermal neutrons, present at all altitudes, and by…”
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Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization by Dilillo, L., Girard, P., Pravossoudovitch, S., Virazel, A., Bastian Hage-Hassan, M.

“…In this paper, we present an exhaustive study on the effects of resistive-open defects in the pre-charge circuits of SRAM memories. In particular, we have…”
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Evaluation of signature-based testing of RF/analog circuits by Zjajo, A., de Gyvez, J.P.

“…Due to its low cost, low test time and reduced test complexity, structural testing is preferred to functional whenever possible. The study presented in this…”
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Stuck-open fault diagnosis with stuck-at model by Xinyue Fan, Moore, W., Hora, C., Gronthoud, G.

“…While most of the fault diagnosis tools are based on gate level fault models, many faults are actually at the transistor level. The stuck-open fault is one of…”
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Coverage of formal properties based on a high-level fault model and functional ATPG by Fummi, F., Pravadelli, G., Toto, F.

“…The use of model checking to validate descriptions of digital systems lacks a coverage metrics. If the set of formal properties defined to prove the…”
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A programmable time measurement architecture for embedded memory characterization by Collins, M., Al-Hashimi, B.M., Ross, N.

“…This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a standalone time measurement…”
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Testing of MEMS-based microsystems by Kerkhoff, H.G.

“…The introduction of MEMS in microsystems is progressing rapidly. The high-volume testing of these multi-domain systems are often relatively cumbersome in…”
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Built-in self-test of molecular electronics-based nanofabrics by Wang, Z., Chakrabarty, K.

“…We propose a built-in self-test (BIST) procedure for nanofabrics based on chemically-assembled electronic nanotechnology. We also present a recovery procedure…”
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Testing of resistive opens in CMOS latches and flip-flops by Champac, V.H., Zenteno, A., Garcia, J.L.

“…Open defects in CMOS memory elements are investigated. The analysis has been carried-out in a class of symmetrical CMOS flip-flop. Main focus is given to high…”
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Design validation of behavioral VHDL descriptions for arbitrary fault models by Fei Xin, Ciesielski, M., Harris, I.G.

“…In this paper we present a flexible automatic test generation framework to detect a variety of design faults in systems with behavioral VHDL descriptions…”
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Energy minimization for hybrid BIST in a system-on-chip test environment by Ubar, R., Shchenova, T., Jervan, G., Peng, Z.

“…This paper addresses the energy minimization problem for system-on-chip testing. We assume a hybrid BIST test architecture where a combination of deterministic…”
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