Search Results - "Euro ASIC '92"

ROTCO: a reverse order test compaction technique by Reddy, L.N., Pomeranz, I., Reddy, S.M.

“…In this paper, the authors consider the problem of reducing the test set sizes for single stuck-at faults in combinational logic circuits. They report on an…”
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Quantifying design quality: a model and design experiments by Aas, E.J., Klingsheim, K., Steen, T.

“…A design process model, focusing on design quality, is presented. Design quality is quantified as the probability that a design object satisfies its…”
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Logic decomposition for programmable gate arrays by Luba, T., Markowski, M., Zbierzchowski, B.

“…In this paper an effective decomposition algorithm for mapping of logic functions onto FPGAs is proposed. The algorithm exploits the symbolic decomposition…”
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Synthesis on multiplexer-based programmable devices using (ordered) binary decision diagrams by Besson, T., Bouzouzou, H., Crastes, M., Soucier, G.

“…Presents synthesis techniques on the Actel multiplexer-based programmable gate arrays. The internal structure of these devices is exploited through binary…”
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Insensitive current-mode biquad implementation based on translinear current conveyors by Fabre, A., Alami, M.

“…An insensitive current-mode filter, implemented from two second generation current conveyors is introduced. The circuit uses four passive components and…”
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An ASIC design for linear predictive coding of speech signals by Wang, Jhing-Fa, Liu, Liang-Ying, Cheng, Chung-Heng, Sheu, Ming-Hwa, Jeang, Yuan-Long, Lee, Jau-Yien

“…In the real-time speech recognition, the predictor coefficients of speech signals are used as the recognizing features and should be computed faster than the…”
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Pipelined TSPC barrel shifter with scan test facilities for VLSI implementation of high speed DSP applications by Pereira, R., Michell, J.A., Solana, J.M.

“…A barrel shifter for high speed data processing is described, together with the test-oriented structure which it has been provided with. The circuit has a…”
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Basic design techniques for both low-power and high-speed ASICs by Piguet, C., von Kaenol, V., Masgonty, J.-M., Perotto, J.-F., Klootsema, R.

“…The authors present several basic techniques to design low-power and high-speed ASIC's. They are based on the need to design as simple circuits as possible…”
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Telescopic layout cells for analog CMOS circuits by Arlt, S., Scarbata, G., Ritter, S., Wisser, C.

“…The authors present a new methodology for designing layout structures of analog building blocks which are used in application specific integrated circuits…”
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DSP ASIC evaluation with fast prototyping by Isoaho, J., Pasanen, J., Nummela, A., Tenhunen, H.

“…Evaluates the utilization of the fast prototyping concept using the practical design experience gained in DSP ASIC integration on the basis of both schematic…”
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FDD based technology mapping for FPGA by Schubert, E., Kebschull, U., Rosenstiel, W.

“…Functional decision diagrams (FDD) are shown to be a very efficient alternative to binary decision diagrams (BDD). FDDs are a representation in the functional…”
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SETIPIC: electrothermal simulator for power integrated circuits in EDGE environment by Hebrard, L., Klingelhofer, C., Jacquemod, G., Boutherin, B., Le Helley, M.

“…The authors present SETIPIC, a software to simulate the electrothermal interactions in the first design steps of power integrated circuits. To give a…”
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Automatic synthesis on table lookup-based PGAs by Babba, B., Crastes, M.

“…Presents a synthesis method for table lookup-based PGAs. It uses three decomposition techniques followed by an area or speed oriented mapping. Among the three…”
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Functional versus random test generation for controllers and finite state machines by Karam, M., Saucier, G.

“…The authors present a functional test generation method for finite state machines based on state graph traversal and evaluates its efficiency by comparing it…”
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Sequential synthesis for table look up PGAs by Murgai, R., Brayton, R.K., Sangiovanni-Vincentelli, A.

“…The algorithms for synthesis onto programmable gate arrays (PGAs) have so far addressed only the combinational logic problem. The authors present two…”
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Context-based ASIC synthesis by Kelem, S.H., Seidel, J.P.

“…The authors describe methods for architecture-specific mapping of high-level functions ASICs. The techniques are demonstrated on field programmable gate arrays…”
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COSIMA: a self-testable simulated annealing processor for universal cost functions by Eschermann, B., Haberl, O., Bringmann, O., Seitz, O.

“…Presents a chip forming the heart of a special purpose coprocessing unit, which accelerates simulated annealing algorithms to solve combinatorial optimization…”
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Modification of logic on ASIC devices by Noone, R.

“…The author describes the modification of control logic on a 1 mu m two layer metal ASIC device. The work was performed using focused ion beam (FIB) techniques…”
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A CMOS ASIC to implement the TC sublayer in the physical layer of the ATM network by Bulone, J., Diaz Nava, M.

“…The line terminator (LT) is designed to support the transmission convergence (TC) sublayer in the physical layer of the ATM network. It provides high speed…”
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The U-VLC VLSI implementation of a universal variable length coder by Descamps, L., Lizin, G.

“…The transform coding scheme is known as one of the most efficient image compression coding methods. The bit rate reduction of the quantified transformed blocks…”
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