Search Results - "Erdmann, Christophe"
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1
A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters
Published in IEEE journal of solid-state circuits (01-01-2015)“…A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35…”
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Journal Article -
2
Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters
Published in IEEE open journal of circuits and systems (2021)“…Non-shaping dynamic element matching (DEM) randomization schemes are widely adopted for wideband Nyquist-rate digital-to-analog converters (DACs) within…”
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Journal Article -
3
An All-Programmable 16-nm RFSoC for Digital-RF Communications
Published in IEEE MICRO (01-03-2018)“…The Xilinx RFSoC is the first product to integrate cutting-edge RF data converters with an FPGA SoC. This breakthrough integration delivers a dramatic…”
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Journal Article -
4
Optimal Driving Signal Extraction for Maximum Efficiency of Dual-Input High Power Amplifiers
Published in IEEE transactions on microwave theory and techniques (04-11-2024)“…Dual-input single-output (DISO) radio frequency (RF) power amplifiers (PAs) have gathered significant interest for highly efficient amplification of modulated…”
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Journal Article -
5
A Robust Search Algorithm of Optimal Driving Signals for Dual-Input High Power Amplifiers
Published in 2024 IEEE/MTT-S International Microwave Symposium - IMS 2024 (16-06-2024)“…This work proposes a robust algorithm to find the optimal driving signals of dual-input single-output Radio Frequency Power Amplifiers with minimal prior…”
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Conference Proceeding -
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A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01-02-2018)“…Direct-RF data converters [1,2] have seen increased adoption in remote-radio-head TX and RX, due to their unparalleled bandwidth and flexibility. However,…”
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Conference Proceeding -
7
A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters
Published in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (01-05-2021)“…This paper presents a programmable amplitude and timing error shaping bandpass dynamic- element-matching (DEM) for Nyquist-rate D/A converters. Amplitude and…”
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Conference Proceeding -
8
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01-02-2017)“…In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by…”
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Conference Proceeding -
9
16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01-02-2017)“…Direct-RF synthesis has gained increasing attention in recent years [1] [2] as it simplifies the transmitter system by eliminating the intermediate frequency…”
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Conference Proceeding -
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6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01-02-2014)“…Data converters are required to interface digital processing engines, for example FPGAs, to the real world. Data conversion is typically accomplished using…”
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Conference Proceeding -
11
A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC
Published in 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (23-11-2020)“…This paper presents a 6 th order programmable bandpass dynamic-element-matching (DEM) that shapes the static mismatch error of a Nyquist DAC for any choice of…”
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Conference Proceeding -
12
A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC
Published in 2018 IEEE Symposium on VLSI Circuits (01-06-2018)“…This work presents direct-RF TX/RX modular tiles for monolithic integration in 16nm FinFET. The TX tile embeds 4 baseband-to-RF signal chains with 14-bit 9GS/s…”
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Conference Proceeding -
13
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET
Published in 2018 IEEE Symposium on VLSI Circuits (01-06-2018)“…A 13bit 5GS/s time-interleaved ADC is described which uses a chopping technique to reduce the effect of interleaved flicker noise spectral artefacts and to…”
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Conference Proceeding -
14
A programmable RFSoC in 16nm FinFET technology for wideband communications
Published in 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01-11-2017)“…In this paper, we present a Programmable SoC device with monolithically integrated RF-ADCs and RF-DACs in a 16nm FinFET process. The device includes quad ARM…”
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Conference Proceeding -
15
Design and characterization of a high-precision resistor ladder test structure
Published in IEEE transactions on semiconductor manufacturing (01-05-2003)“…A new subsite stepped multiresistor test structure is introduced. This test structure is used for studying and improving small resistance mismatch patterns in…”
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Journal Article Conference Proceeding