Reliability issues of silicon LSIs facing 100-nm technology node
Reliability issues regarding scaled silicon devices are reviewed from the viewpoint of the 100-nm technology node. Topics covered include hot carrier degradation, negative bias-temperature instability, boron penetration, interface properties of a high- k dielectric film, and stress-induced leakage c...
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| Published in: | Microelectronics and reliability Vol. 42; no. 4; pp. 493 - 506 |
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| Main Authors: | , , , , , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
Elsevier Ltd
01-04-2002
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| Online Access: | Get full text |
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| Summary: | Reliability issues regarding scaled silicon devices are reviewed from the viewpoint of the 100-nm technology node. Topics covered include hot carrier degradation, negative bias-temperature instability, boron penetration, interface properties of a high-
k dielectric film, and stress-induced leakage current of a floating-gate-type non-volatile memory. Soft error by terrestrial neutrons is also discussed as an emerging reliability issue. In addition, copper-wiring reliability is extensively reviewed from the viewpoint of further miniaturization. |
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| Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| ISSN: | 0026-2714 1872-941X |
| DOI: | 10.1016/S0026-2714(02)00029-X |