Search Results - "ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference"

A 30fJ/comparison dynamic bias comparator by Bindra, Harijot Singh, Lokin, Chris E., Annema, Anne-Johan, Nauta, Bram

“…A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type…”
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A 400 MHz 4.5 nW −63.8 dBm sensitivity wake-up receiver employing an active pseudo-balun envelope detector by Wang, Po-Han Peter, Haowei Jiang, Li Gao, Pinar Sen, Young-Han Kim, Rebeiz, Gabriel M., Mercier, Patrick P., Hall, Drew A.

“…A 402-405 MHz MICS-band wake-up receiver is presented that achieves -63.8 dBm sensitivity at 4.5 nW. High sensitivity at 400 MHz is accomplished via an 18.5 dB…”
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A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology by Hechen Wang, Dai, Fa Foster

“…This paper presents a time-to-digital (TDC) design with large detectable range and fine resolution, combining a ring TDC with a 2-dimentional (2D) Vernier TDC…”
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OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators by Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Rui Ma, Peiyong Zhang, Xiaolang Yan, Yu Wang, Mingyu Wang, Hao Min, Shi, Richard C.-J

“…A deep learning processor with 8 gated recurrent neural network (RNN) accelerators is proposed in this paper. It features on-chip incremental learning by…”
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A 1.02nW PMOS-only, trim-free current reference with 282ppm/°C from −40°C to 120°C and 1.6% within-wafer inaccuracy by Qing Dong, Inhee Lee, Kaiyuan Yang, Blaauw, David, Sylvester, Dennis

“…A 1.02nW current reference is designed with only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation…”
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A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array by Mingu Kang, Gonugondla, Sujan K., Shanbhag, Naresh R.

“…This paper presents IC realization of a random forest (RF) machine learning classifier. Algorithm-architecture-circuit is co-optimized to minimize the…”
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A 1-MHz on-chip relaxation oscillator with comparator delay cancelation by Mikulic, Josip, Schatzberger, Gregor, Baric, Adrijan

“…In this work, an improved topology of a relaxation oscillator is proposed, dealing with the non-idealities of the comparator stage. The oscillator test chips,…”
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A CMOS current driver with built-in common-mode signal reduction capability for EIT by Yu Wu, Dai Jiang, Langlois, Peter, Bayford, Richard, Demosthenous, Andreas

“…This paper presents an integrated fully differential current driver for wearable multi-frequency electrical impedance tomography (EIT). The integrated circuit…”
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A 24 μW 38.51 mΩrms resolution bio-impedance sensor with dual path instrumentation amplifier by Kwantae Kim, Kiseok Song, Kyeongryeol Bong, Jaehyuk Lee, Kwonjoon Lee, Yongsu Lee, Unsoo Ha, Hoi-Jun Yoo

“…This paper presents a low power, high resolution bio-impedance sensor IC for respiration monitoring application. It contains the dual path instrumentation…”
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A transimpedance amplifier using a widely tunable PVT-independent pseudo-resistor for high-performance current sensing applications by Djekic, Denis, Fantner, Georg, Behrends, Jan, Lips, Klaus, Ortmanns, Maurits, Anders, Jens

“…In this paper, we present a pseudo-resistor-based transimpedance amplifier (TIA) whose transimpedance value is PVT-independent and continuously tuneable over a…”
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A low-noise reconfigurable full-duplex front-end with self-interference cancellation and harmonic-rejection power amplifier for low power radio applications by Tong Zhang, Yongdong Chen, Chenxi Huang, Rudell, Jacques C.

“…A low-power radio analog front-end which includes a self-interference (SI) cancellation circuit and a harmonic-rejection power amplifier (HRPA), is proposed to…”
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A HBT-based 300 MHz-12 GHz blocker-tolerant mixer-first receiver by Ying, Robin, Morton, Matthew, Molnar, Alyosha

“…A 300 MHz-12 GHz HBT-based mixer-first receiver in 130 nm BiCMOS is presented. The mixer core is composed of four SiGe HBTs driven by quadrature LO pulses with…”
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Overview of 5G requirements and future wireless networks by Mattisson, Sven

“…In this presentation we review the evolution of radio access networks and introduce 5G, based on the current plans and expectations, as reported in the recent…”
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An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications by Giterman, Robert, Fish, Alexander, Geuli, Narkis, Mentovich, Elad, Burg, Andreas, Teman, Adam

“…Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional SRAM, due to its high-density, low-leakage, and inherent 2-ported operation,…”
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A 420 fW self-regulated 3T voltage reference generator achieving 0.47%/V line regulation from 0.4-to-1.2 V by Hui Wang, Mercier, Patrick P.

“…This paper presents a constant with temperature (CWT) voltage reference generator (VRG) that utilizes only regular transistors in standard CMOS technology. By…”
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An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications by Changhyeon Kim, Kyeongryeol Bong, Injoon Hong, Kyuho Lee, Sungpill Choi, Hoi-Jun Yoo

“…A new face detection SoC integrating CIS array with low-power face detector on a single chip in analog-digital mixed-mode is proposed for ultra-low-power…”
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A 25 mV-startup cold start system with on-chip magnetics for thermal energy harvesting by Garcha, Preet, El-Damak, Dina, Desai, Nachiket, Troncoso, Jorge, Mazotti, Erika, Mullenix, Joyce, Tang, Shaoping, Trombley, Django, Buss, Dennis, Lang, Jeffrey, Chandrakasan, Anantha

“…Thermal energy harvesting systems use boost converters for high-efficiency low voltage operation, but lack the ability for low voltage startup without off-chip…”
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A multi-sensor and parallel processing SoC for wearable and implantable telemetry systems by Schonle, P., Rovere, G., Glaser, F., Bosser, J., Brun, N., Han, X., Burger, T., Fateh, S., Wang, Q., Benini, L., Huang, Q.

“…We report a system-on-chip (SoC) realised in 130nm CMOS for implantable telemetry systems and mobile health applications featuring 6 neural stimulation…”
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A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS by Ramkaj, Athanasios, Strackx, Maarten, Steyaert, Michiel, Tavernier, Filip

“…A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and…”
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A <25 μW CMOS monolithic photoplethysmographic sensor with distributed 1b delta-sigma light-to-digital convertor by Hyung-Gi Kim, Dong-Woo Jee

“…This paper presents CMOS monolithic PPG sensor with distributed 1b delta-sigma light-to-digital convertor (LDC). Proposed unbiased photodiode (PD) based…”
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