Search Results - "Du Bois, Kristof"

The Intel® Programmable and Integrated Unified Memory Architecture (PIUMA) Graph Analytics Processor by Aananthakrishnan, Sriram, Abedin, Shamsul, Cave, Vincent, Checconi, Fabio, Du Bois, Kristof, Eyerman, Stijn, Fryman, Joshua B., Heirman, Wim, Howard, Jason, Hur, Ibrahim, Jain, Samkit, Landowski, Marek M., Ma, Kevin, Nelson, Jarrod, Pawlowski, Robert, Petrini, Fabrizio, Szkoda, Sebastian, Tayal, Sanjaya, Tithi, Jesmin Jahan, Vandriessche, Yves

“…High performance large scale graph analytics are essential to timely analyze relationships in big data sets. Conventional processor architectures suffer from…”
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RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors by Heirman, Wim, Eyerman, Stijn, Du Bois, Kristof, Hur, Ibrahim

“…Architectural studies of the cache and memory hierarchy need a fast simulation model for the processor core that accurately conveys the impact of memory…”
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Multi-Stage CPI Stacks by Eyerman, Stijn, Heirman, Wim, Du Bois, Kristof, Hur, Ibrahim

“…CPI stacks are an intuitive way to visualize processor core performance bottlenecks. However, they often do not provide a full view on all bottlenecks, because…”
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Many-Core Graph Workload Analysis by Eyerman, Stijn, Heirman, Wim, Du Bois, Kristof, Fryman, Joshua B., Hur, Ibrahim

“…Graph applications have specific characteristics that are not common in other application domains and therefore require thorough analysis to guide future graph…”
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Accurate and Scalable Many-Node Simulation by Eyerman, Stijn, Heirman, Wim, Bois, Kristof Du, Hur, Ibrahim

“…Accurate performance estimation of future many-node machines is challenging because it requires detailed simulation models of both node and network. However,…”
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Projecting Performance for PIUMA using Down-Scaled Simulation by Eyerman, Stijn, Heirman, Wim, Demir, Yigit, Du Bois, Kristof, Hur, Ibrahim

“…Programmable Integrated Unified Memory Architecture (PIUMA) is Intel's novel graph analysis optimized processor architecture, targeted at efficiently executing…”
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Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks by Eyerman, Stijn, Heirman, Wim, Du Bois, Kristof, Hur, Ibrahim

“…CPI stacks are an intuitive way to visualize processor core performance bottlenecks. However, they often do not provide a full view on all bottlenecks, because…”
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Analyzing the scalability of managed language applications with speedup stacks by Sartor, Jennifer B., Bois, Kristof Du, Eyerman, Stijn, Eeckhout, Lieven

“…Understanding the reasons why multi-threaded applications do not achieve perfect scaling on modern multicore hardware is challenging. Furthermore, more and…”
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Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications by Eyerman, S., Du Bois, Kristof, Eeckhout, L.

“…Multi-threaded workloads typically show sublinear speedup on multi-core hardware, i.e., the achieved speedup is not proportional to the number of cores and…”
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PIUMA: Programmable Integrated Unified Memory Architecture by Aananthakrishnan, Sriram, Ahmed, Nesreen K, Cave, Vincent, Cintra, Marcelo, Demir, Yigit, Bois, Kristof Du, Eyerman, Stijn, Fryman, Joshua B, Ganev, Ivan, Heirman, Wim, Hoppe, Hans-Christian, Howard, Jason, Hur, Ibrahim, Kodiyath, MidhunChandra, Jain, Samkit, Klowden, Daniel S, Landowski, Marek M, Montigny, Laurent, More, Ankit, Ossowski, Przemyslaw, Pawlowski, Robert, Pepperling, Nick, Petrini, Fabrizio, Sikora, Mariusz, Seshasayee, Balasubramanian, Smith, Shaden, Szkoda, Sebastian, Tayal, Sanjaya, Tithi, Jesmin Jahan, Vandriessche, Yves, Wrosz, Izajasz P

“…High performance large scale graph analytics is essential to timely analyze relationships in big data sets. Conventional processor architectures suffer from…”
Get full text