Search Results - "Drijbooms, C."

Copper plating for 3D interconnects by Radisic, A., Lühn, O., Philipsen, H.G.G., El-Mekki, Z., Honore, M., Rodet, S., Armini, S., Drijbooms, C., Bender, H., Ruythooren, W.

“…In this paper we report on Cu plating of through-silicon-vias (TSV-s) using in-house made acidic Cu bath with model additives (SPS, PEG, and JGB). Although the…”
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Structural characterization of through silicon vias by Bender, H., Drijbooms, C., Van Marcke, P., Geypen, J., Philipsen, H. G. G., Radisic, A.

“…Different milling strategies for the structural characterization of through silicon vias on silicon wafers and in stacked dies are examined. For investigation…”
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Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node by Gupta, A., Mertens, H., Tao, Z., Demuynck, S., Bommels, J., Arutchelvan, G., Devriendt, K., Pedreira, O. Varela, Ritzenthaler, R., Wang, S., Radisic, D., Kenis, K., Teugels, L., Sebaai, F., Lorant, C., Jourdan, N., Chan, B. T., Zahedmanesh, H., Subramanian, S., Schleicher, F., Hopf, T., Peter, A., Rassoul, N., Debruyn, H., Demonie, I., Siew, Y., Chiarella, T., Briggs, B., Zhou, D., Rosseel, E., De Keersgieter, A., Capogreco, E., Litta, E. Dentoni, Boccardi, G., Baudot, S., Mannaert, G., Bontemps, N., Sepulveda, A., Mertens, S., Kim, M. S., Dupuy, E., Vandersmissen, K., Paolillo, S., Yakimets, D., Chehab, B., Favia, P., Drijbooms, C., Cousserier, J., Jaysankar, M., Lazzarino, F., Morin, P., Sanchez, E., Mitard, J., Wilson, C., Holsteyns, F., Tokei, Z., Horiguchi, N.

“…Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of…”
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Towards Improved Nanosheet-Based Complementary Field Effect Transistor (CFET) Performance Down to 42nm Contacted Gate Pitch by Chiarella, T., Matagne, P., Mertens, H., Hosseini, M., Zhou, X., Eyben, P., Arimura, H., Gupta, A., Richard, O., Drijbooms, C., Caluwaerts, R., Horiguchi, N., Mitard, J.

“…This work provides keys for optimizing nanosheet-based monolithic Complementary Field-Effect Transistors below 50nm gate pitch, relevant to industry "sub-nm"…”
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Materials characterization of WNxCy, WNx and WCx films for advanced barriers by Volders, H, Tokei, Z, Bender, H, Brijs, B, Caluwaerts, R, Carbonell, L, Conard, T, Drijbooms, C, Franquet, A, Garaud, S, Hoflijk, I, Moussa, A, Sinapi, F, Travaly, Y, Vanhaeren, D, Vereecke, G, Zhao, C, Li, W-M, Sprey, H

“…A ternary WNxCy system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 deg C in a process sequence using tungsten hexafluoride…”
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A Correlative Analysis Flow for Electrical and Structural Characterization of IGZO Transistors by Magnarin, L., Agati, M., Belmonte, A., Subhechha, S., Rassoul, N., Drijbooms, C., Dekkers, H., Celano, U.

“…We report on a custom sample preparation flow for correlative metrology. This is applied here to the electrical, structural, and compositional analysis of…”
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Reverse tip sample scanning for precise and high-throughput electrical characterization of advanced nodes by Celano, U., Hantschel, T., Boehme, T., Kanniainen, A., Wouters, L., Bender, H., Bosman, N., Drijbooms, C., Folkersma, S., Paredis, K., Vandervorst, W., der Heide, P. van

“…A new method is proposed to enable high-throughput and high-resolution electrical atomic force microscopy in nanoelectronics. Using a reversed pathway of…”
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Materials characterization of WN x C y , WN x and WC x films for advanced barriers by Volders, H., Tökei, Z., Bender, H., Brijs, B., Caluwaerts, R., Carbonell, L., Conard, T., Drijbooms, C., Franquet, A., Garaud, S., Hoflijk, I., Moussa, A., Sinapi, F., Travaly, Y., Vanhaeren, D., Vereecke, G., Zhao, C., Li, W.-M., Sprey, H., Jonas, A.M.

“…A ternary WN x C y system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride…”
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Degradation and failure analysis of copper and tungsten contacts under high fluence stress by Kauerauf, T, Butera, G, Croes, K, Demuynck, S, Wilson, C J, Roussel, P, Drijbooms, C, Bender, H, Lofrano, M, Vandevelde, B, Tökei, Zsolt, Groeseneken, G

“…The reliability of Cu and W contacts under high fluence stress mimicking source/drain contacts in the on-state of a transistor is evaluated. We use Kelvin…”
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Materials characterization of WNxCy, WNxand WCx films for advanced barriers by VOLDERS, H, TOKEI, Z, HOFLIJK, I, MOUSSA, A, SINAPI, F, TRAVALY, Y, VANHAEREN, D, VEREECKE, G, ZHAO, C, LI, W.-M, SPREY, H, JONAS, A. M, BENDER, H, BRIJS, B, CALUWAERTS, R, CARBONELL, L, CONARD, T, DRIJBOOMS, C, FRANQUET, A, GARAUD, S

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3D-carrier profiling in FinFETs using scanning spreading resistance microscopy by Mody, J., Zschatzsch, G., Kolling, S., De Keersgieter, A., Eneman, G., Kambham, A. K., Drijbooms, C., Schulze, A., Chiarella, T., Horiguchi, N., Hoffmann, T-Y, Eyben, P., Vandervorst, W.

“…In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate…”
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Scanning spreading resistance microscopy for carrier profiling beyond 32nm node by Mody, J., Zschatzsch, G., Kolling, S., De Keersgieter, A., Eneman, G., Kambham, A. K., Drijbooms, C., Schulze, A., Chiarella, T., Horiguchi, N., Eyben, P., Vandervorst, W.

“…With the continued scaling of CMOS devices down to 32nm node and beyond, device performance is very sensitive to the lateral diffusion mechanisms influencing…”
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