Search Results - "Doria, Rodrigo Trevisoli"

Junctionless Multiple-Gate Transistors for Analog Applications by Doria, R. T., Pavanello, M. A., Trevisoli, R. D., de Souza, M., Chi-Woo Lee, Ferain, I., Akhavan, N. D., Ran Yan, Razavi, P., Ran Yu, Kranti, A., Colinge, J.

“…This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited…”
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Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors by Trevisoli, R. D., Doria, R. T., de Souza, M., Das, S., Ferain, I., Pavanello, M. A.

“…This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation…”
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Analysis of the leakage current in junctionless nanowire transistors by Trevisoli, Renan, Trevisoli Doria, Rodrigo, de Souza, Michelly, Antonio Pavanello, Marcelo

“…This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with…”
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Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates by Doria, Rodrigo Trevisoli, Martino, João Antonio, Simoen, Eddy, Claeys, Cor, Pavanello, Marcelo Antonio

“…► Low-frequency noise analysis of 0° and 45° substrate rotated FinFETs is carried out. ► Substrate rotation has not affected the 1/f noise. ► Substrate…”
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Cross-coupling effects in common-source current mirrors composed by UTBB transistors by José da Costa, Fernando, Trevisoli, Renan, Trevisoli Doria, Rodrigo

“…•Study performed through 3D numerical simulations validated with experimental data.•Analysis of the coupling effects in current mirrors composed by UTBB as…”
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Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors by Trevisoli, Renan, Trevisoli Doria, Rodrigo, de Souza, Michelly, Pavanello, Marcelo Antonio

“…The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental…”
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Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors by Trevisoli, Renan, Trevisoli Doria, Rodrigo, de Souza, Michelly, Barraud, Sylvain, Vinet, Maud, Pavanello, Marcelo Antonio

“…This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is…”
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A New Method for Series Resistance Extraction of Nanometer MOSFETs by Trevisoli, Renan, Trevisoli Doria, Rodrigo, de Souza, Michelly, Barraud, Sylvain, Vinet, Maud, Casse, Mikael, Reimbold, Gilles, Faynot, Olivier, Ghibaudo, Gerard, Pavanello, Marcelo Antonio

“…This paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic…”
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Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors by Costa, Fernando Jose da, Trevisoli, Renan, Doria, Rodrigo Trevisoli

“…The main objective of this work is to present an analysis of the performance of Ultra-Thin-Body and Buried Oxide transistors working as Ultra-Low-Power and…”
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A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors by Trevisoli, Renan Doria, Doria, Rodrigo Trevisoli, de Souza, Michelly, Pavanello, Marcelo Antonio

“…► The equality of the drift and diffusion components of the drain current was defined as threshold condition. ► A methodology for the threshold voltage…”
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The zero temperature coefficient in junctionless nanowire transistors by Trevisoli, Renan Doria, Doria, Rodrigo Trevisoli, Souza, Michelly de, Das, Samaresh, Ferain, Isabelle, Pavanello, Marcelo Antonio

“…This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which…”
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Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS by Doria, Rodrigo Trevisoli, Simoen, Eddy, Claeys, Cor, Martino, João Antonio, Pavanello, Marcelo Antonio

“…► HD3 of 2-MOS structures composed by FinFETs reduces with the raise of the gate bias. ► HD3 reduction is more pronounced in narrower and longer devices. ► HD3…”
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Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors by Trevisoli, Renan, Doria, Rodrigo Trevisoli, Barraud, Sylvain, Pavanello, Marcelo Antonio

“…The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire…”
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Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors by Trevisoli, Renan, Pavanello, Marcelo Antonio, Capovilla, Carlos Eduardo, Barraud, Sylvain, Doria, Rodrigo Trevisoli

“…This article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different…”
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Non-linearity analysis of triple gate SOI nanowires MOSFETS by Cardoso Paz, Bruna, Trevisoli Doria, Rodrigo, Casse, Mikael, Barraud, Sylvain, Reimbold, Gilles, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo Antonio

“…This work aims to explore the harmonic distortion of triple gate SOI nanowires MOSFETs, considering long channel devices operating in saturation regime as…”
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On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration by de Souza, Michelly, Flandre, Denis, Doria, Rodrigo Trevisoli, Trevisoli, Renan, Pavanello, Marcelo Antonio

“…This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC)…”
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Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range by Pavanello, Marcelo Antonio, Cerdeira, Antonio, Doria, Rodrigo Trevisoli, Ribeiro, Thales Augusto, Ávila-Herrera, Fernando, Estrada, Magali

“…This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for…”
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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization by Doria, Rodrigo Trevisoli, Trevisoli, Renan, de Souza, Michelly, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo Antonio

“…This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire…”
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Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors by Trevisoli, Renan, Doria, Rodrigo Trevisoli, de Souza, Michelly, Pavanello, Marcelo Antonio

“…This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire…”
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Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation by d'Oliveira, Ligia Martins, Trevisoli Doria, Rodrigo, Pavanello, Marcelo A., de Souza, Michelly, Flandre, Denis

“…This paper presents an experimental analysis of the harmonic distortion of asymmetric self-cascode (A-SC) association of SOI transistors. This goal is achieved…”
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