A Compression Improvement Technique for Low-Power Scan Test Data

The huge test data volume, test time and power consumption are major problems in system-on-a-chip testing. To tackle those problems, we propose a new test data compression technique. Initially, don't-cares in a pre-computed test cube set are assigned to reduce the test power consumption, and th...

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Bibliographic Details
Published in:	TENCON 2006 - 2006 IEEE Region 10 Conference pp. 1 - 4
Main Authors:	Jaehoon Song, Hyunbean Yi, Doochan Hwang, Sungju Park
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-11-2006
Subjects:	Circuit testing Computer science Data engineering Energy consumption Filling Power engineering and energy System testing System-on-a-chip Test data compression Test pattern generators
Online Access:	Get full text
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Description
Summary:	The huge test data volume, test time and power consumption are major problems in system-on-a-chip testing. To tackle those problems, we propose a new test data compression technique. Initially, don't-cares in a pre-computed test cube set are assigned to reduce the test power consumption, and then, the fully specified low-power test data is transformed to improve compression efficiency by neighboring bitwise exclusive-or (NB-XOR) scheme. Finally, the transformed test set is compressed to reduce both the test equipment storage requirements and test application time
ISBN:	9781424405480 1424405483
ISSN:	2159-3442 2159-3450
DOI:	10.1109/TENCON.2006.344040