Search Results - "Doedel, W."

Chemical Mechanical Polishing for Planarisation of Advanced IC Processes by Lifka, H., Doedel, W., Souts, T., Woerlee, P. H.

“…An CMP process will be presented which is optimised for low layout sensitivity and good uniformity. The best results were obtained by using a stack of two…”
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First Look at Across-chip Performance Variation Using Non-Contact, Performance-Based Metrology by Babazadeh, M., Estabil, J., Borot, B., Johnson, G., Pakdaman, N., Doedel, W., Vickers, J., Steinbrueck, G., Galvier, J.

“…We report on the first non-contact, non-destructive performance measurements of embedded ring oscillators. Measurements are made on inside the die active area…”
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Feasibility of a novel modular approach for planarization of a submicron triple-level metal CMOS process by Parekh, N., Butler, A., Doedel, W., Heesters, W., Forester, L.

“…The feasibility of a triple-level-metal submicron CMOS process using proven and manufacturable modules is demonstrated. While resist etchback and a silicate…”
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Development of a three-layer metal backend process for application to a submicron CMOS logic process by Forester, L., Doedel, W., Osinski, K., Heesters, W.

“…A three-layer metal process for application to a submicron logic process has been developed. The development was carried out in two phases. In phase 1, the…”
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