Search Results - "Dingyou Zhang"

Process Development and Optimization for 3 \mu \text High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level by Dingyou Zhang, Smith, Daniel, Kumarapuram, Gopal, Giridharan, Rudy, Kakita, Shinichiro, Rabie, Mohamed A., Peijie Feng, Edmundson, Holly, England, Luke

“…This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical…”
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Process development and optimization for high-aspect ratio through-silicon via (TSV) etch by Gopalakrishnan, Kumarapuram, Peddaiahgari, Anurag, Smith, Daniel, Dingyou Zhang, England, Luke

“…Etch is one of the most critical processes for high-aspect ratio TSV as it defines the profile and wafer level depth uniformity of TSV, thus having a great…”
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A novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment by Chen, Qianwen, Zhang, Dingyou, Xu, Zheng, Beece, Adam, Patti, Robert, Tan, Zhimin, Wang, Zheyao, Liu, Litian, Lu, Jian-Qiang

“…This paper reports a novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment. The key unit process steps,…”
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Leaf Potential Productivity at Different Canopy Levels in Densely-planted and Intermediately-thinned Apple Orchards by SUN, Ying, ZHANG, Yin, JIANG, Yuanmao, SONG, Kai, GAO, Juhong, ZHANG, Dingyou, ZHANG, Jixiang

“…Most apple orchards in the apple production districts in China were densely planted with vigorous rootstocks during the 1980s. These orchards have suffered…”
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Methodology to estimate TSV film thickness using a novel inline "adaptive pattern registration" method by Manikonda, Shravanthi L., Dingyou Zhang, Giridharan, Rudy R., Bello, Abner, Jun Song

“…A novel "adaptive pattern registration" method is developed which gives a reliable estimate of various film thickness in a wafer level TSV. The film thickness…”
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Evaluation of fabrication process for a novel Chip-to-Wafer (C2W) 3D integration approach using an alignment template by Dingyou Zhang, Jian-Qiang Lu

“…We proposed a novel Chip-to-Wafer (C2W) 3D integration approach using an alignment template and well-controlled wafer-level bonding. With an alignment template…”
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New interferometric measurement technique for small diameter TSV by Timoney, Padraig, Fisher, Daniel, Yeong-Uk Ko, Vaid, Alok, Thangaraju, Sarasvathi, Smith, Daniel, Kamineni, Himani, Dingyou Zhang, Alapati, Ramakanth, Wonwoo Kim, Ke Xiao, Edmundson, Holly, Smith, Nigel, Peterson, Brennan, Amin, Hemant, Peak, Jonathan, Johnson, Tim

“…High aspect ratio through silicon vias (TSV) present a challenge for measurement of bottom critical dimension (BCD) and depth. TSVs smaller than 5 micron…”
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TSV residual Cu step height analysis by white light interferometry for 3D integration by Smith, Daniel, Singh, Sanjeev, Ramnath, Yudesh, Rabie, Mohamed, Dingyou Zhang, England, Luke

“…Cu pumping, or the extrusion of Cu out of a TSV after being subjected to high temperature conditions, is one of the highest risk failure modes to be overcome…”
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Backside TSV protrusion induced by thermal shock and thermal cycling by Dingyou Zhang, Hummler, Klaus, Smith, Larry, Lu, James Jian-Qiang

“…This paper reports on thermal-mechanical failures of through-silicon-vias (TSVs), in particular, for the first time, the protrusions at the TSV backside, which…”
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Room temperature ALD oxide liner for TSV applications by Dingyou Zhang, Smith, Daniel, Lundeen, David, Kakita, Shinichiro, England, Luke

“…To date, Plasma Enhanced Chemical Vapor Deposition (PECVD) O3/TEOS has been the prevalent dielectric liner for TSV applications. This process typically results…”
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Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network by Zheng Xu, Beece, A, Dingyou Zhang, Qianwen Chen, Kuan-neng Chen, Rose, K, Jian-Qiang Lu

“…Through-strata-via (TSV) is regarded as a critical component in 3D integration that extends Moore's Law. This paper reports on TSV crosstalk performance under…”
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Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding by Qianwen Chen, Dingyou Zhang, Zheyao Wang, Litian Liu, Lu, James Jian-Qiang

“…This paper presents on a novel chip-to-wafer (C2W) three-dimensional (3D) integration technology with well-controlled template alignment and wafer-level…”
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Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture by Zheng Xu, Beece, A, Dingyou Zhang, Qianwen Chen, Rose, K, Jian-Qiang Lu

“…3D integration is expected to lead to a semiconductor industry paradigm shift due to its tremendous benefits to performance, data bandwidth, functionality,…”
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Processing material evaluation and ultra-wideband modeling of through-strata-via (TSV) in 3D integrated circuits and systems by Zheng Xu, Beece, A, Dingyou Zhang, Qianwen Chen, Rose, K, Lu, James Jian-Qiang

“…Since the conventional planar ICs encountered many physical, technological and economic bottlenecks, 3D integration by stacking and connecting function blocks…”
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Process Development and Optimization for 3 [Formula Omitted] High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level by Zhang, Dingyou, Smith, Daniel, Kumarapuram, Gopal, Giridharan, Rudy, Kakita, Shinichiro, Rabie, Mohamed A, Feng, Peijie, Edmundson, Holly, England, Luke

“…This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 [Formula Omitted] top…”
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Challenges to via middle TSV integration at sub-28nm nodes by Kamineni, Himani Suhag, Kannan, Sukeshwar, Alapati, Ramakanth, Thangaraju, Sarasvathi, Smith, Daniel, Dingyou Zhang, Shan Gao

“…This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented…”
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A Novel Chip-to-Wafer 3D Integration Technology by Zhang, Dingyou

“…Three-dimensional (3D) integration, which can stack different materials, technologies and functional components vertically, is a promising technology to…”
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A Novel Chip-to-Wafer 3D Integration Technology by Zhang, Dingyou

“…Three-dimensional (3D) integration, which can stack different materials, technologies and functional components vertically, is a promising technology to…”
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Study of Polyimide in Chip Package Interaction for Flip-Chip Cu-Pillar Packages by Wang, Wei, Zhang, Dingyou, Sun, Yangyang, Rae, David, Zhao, Lily, Zheng, Jiantao, Schwarz, Mark, Shah, Milind, Syed, Ahmer

“…Chip-package interaction (CPI) is a key area for achieving robust copper bump interconnection in flip-chip packages. Polyimide (PI) has been widely used in…”
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