Search Results - "Dimitroulakos, G."
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Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System
Published in IEEE transactions on very large scale integration (VLSI) systems (01-12-2007)“…This paper presents performance improvements and energy savings from mapping real-world benchmarks on an embedded single-chip platform that includes…”
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A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000
Published in Integration (Amsterdam) (01-09-2005)“…In this paper, the design and implementation of an optimized hardware architecture in terms of speed and memory requirements for computing the tile-based 2D…”
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A Framework for Data Partitioning for C++ Data-Intensive Applications
Published in Design automation for embedded systems (01-06-2004)“…We present an automated framework that partitions the code and data types for the needs of data management in an object-oriented source code. The goal is to…”
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An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
Published in 2005 IEEE International Symposium on Circuits and Systems (ISCAS) (2005)“…The paper presents a memory-conscious mapping methodology of computationally intensive applications on coarse-grain reconfigurable arrays. By exploiting the…”
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An ultra high speed architecture for VLSI implementation of hash functions
Published in 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 (2003)“…Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years…”
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Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays
Published in 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)“…It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus…”
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Conference Proceeding -
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Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware
Published in 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)“…In this paper, we propose a hardware/software partitioning method for improving applications' performance in embedded systems. Critical software parts are…”
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Accelerating applications by mapping critical kernels on coarse-grain reconfigurable hardware in hybrid systems
Published in 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) (2005)“…In this paper, we propose a method for speeding-up applications by partitioning them between the reconfigurable hardware blocks of different granularity and…”
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Speedups from partitioning software kernels to FPGA hardware in embedded SoCs
Published in IEEE Workshop on Signal Processing Systems Design and Implementation, 2005 (2005)“…This paper presents a hardware/software partitioning methodology for improving performance in single-chip systems comprised by processor and reconfigurable…”
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An efficient VLSI implementation for forward and inverse wavelet transform for JPEG2000
Published in 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628) (2002)“…In this paper a new methodology for building up filters for the JPEG2000 standard is presented. The proposed filter architectures can be applied efficiently…”
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Power aware data type refinement on the HIPERLAN/2
Published in 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 (2003)“…A power aware data type refinement performed on the data link control layer of the HIPERLAN 2 protocol is presented. Applying static and dynamic analysis on…”
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Conference Proceeding -
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Mapping DSP applications on processor/coarse-grain reconfigurable array architectures
Published in 2006 IEEE International Symposium on Circuits and Systems (ISCAS) (2006)“…Results from mapping five real-world DSP applications on a system-on-chip that incorporates coarse-grain reconfigurable hardware with an instruction-set…”
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13
Resource constrained modulo scheduling for coarse-grained reconfigurable arrays
Published in 2006 IEEE International Symposium on Circuits and Systems (ISCAS) (2006)“…It is widely known that bandwidth limitations degrade parallel systems' performance. This paper presents a mapping methodology for coarse-grain reconfigurable…”
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Performance improvements from partitioning applications to FPGA hardware in embedded SoCs
Published in The Journal of supercomputing (01-02-2006)Get full text
Journal Article -
15
A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard
Published in 2005 IEEE International Symposium on Circuits and Systems (ISCAS) (2005)“…The design and implementation of an efficient hardware architecture in terms of speed and memory requirements for computing the tile-based two-dimensional…”
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Conference Proceeding -
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MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations
Published in Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing (01-10-2012)“…In this paper, we present MEMSCOPT, a source-to-source compiler incorporated in a system level design tool chain for dynamic code analysis and loop…”
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XMSIM: A tool for early memory hierarchy evaluation
Published in Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing (01-10-2012)“…In this demonstration we present the usage of XMSIM, a tool for memory hierarchy evaluation of multimedia applications. The input is a high level C code…”
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XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation
Published in 2010 IEEE Computer Society Annual Symposium on VLSI (01-07-2010)“…This paper presents a memory hierarchy evaluation framework for multimedia applications. It takes as input a high level C code application description and a…”
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Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays
Published in 2008 International Symposium on System-on-Chip (01-11-2008)“…The efficiency of a Coarse Grained Reconfigurable Array architecture in terms of performance and hardware cost is hard to be determined. Until now, few case…”
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Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
Published in Proceedings 20th IEEE International Parallel & Distributed Processing Symposium (2006)“…In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained…”
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