Search Results - "Dimitriou, Georgios"

Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs by Tragoudaras, Antonios, Stoikos, Pavlos, Fanaras, Konstantinos, Tziouvaras, Athanasios, Floros, George, Dimitriou, Georgios, Kolomvatsos, Kostas, Stamoulis, Georgios

“…Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in…”
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Phytochemical screening of Psidium guajava and Carica papaya leaves aqueous extracts cultivated in Greece and their potential as health boosters by Dimitrios D. Ntakoulas, Ioannis N. Pasias, Kalomoira G. Raptopoulou, Georgios Dimitriou, Charalampos Proestos

“…Aim: The scope of the present study was to investigate the phytochemical profile of Psidium guajava and Carica papaya leaves aqueous extracts, from plants…”
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Myocarditis and pericarditis in association with COVID-19 mRNA-vaccination: cases from a regional pharmacovigilance centre by Istampoulouoglou, Ioanna, Dimitriou, Georgios, Späni, Selina, Christ, Andreas, Zimmermanns, Barbara, Koechlin, Sarah, Stoeckmann, Oliver, Winterhalder, Clemens, Marono, David, Toma, Valeriu, Leuppi-Taegtmeyer, Anne B

“…In this article we summarize suspected adverse events following immunization (AEFI) of pericarditis, myocarditis and perimyocarditis that were reported by our…”
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Development and Implementation of an e-Trigger Tool for Adverse Drug Events in a Swiss University Hospital by El Saghir, Amina, Dimitriou, Georgios, Scholer, Miriam, Istampoulouoglou, Ioanna, Heinrich, Patrick, Baumgartl, Klaus, Schwendimann, René, Bassetti, Stefano, Leuppi-Taegtmeyer, Anne

“…The purpose of the study was to develop and implement an institution-specific trigger tool based on the Institute for Healthcare Improvement medication module…”
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Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework by Dossis, Michael, Dimitriou, Georgios

“…Academic High-level Synthesis tools like CustomCoprocessorsCompiler have recently evolved in new versions with expanded functionality and more aggressive…”
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Global and Pointer Variables in High-Level Synthesis by Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…High-level synthesis (HLS) has been an important tool in digital circuit design for more than two decades, especially for processor components like…”
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From Cyber Terrorism to Cyber Peacekeeping: Are we there yet? by Papathanasaki, Maria, Dimitriou, Georgios, Maglaras, Leandros, Vasileiou, Ismini, Janicke, Helge

“…In Cyberspace nowadays, there is a burst of information that everyone has access. However, apart from the advantages the Internet offers, it also hides…”
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Near Data Processing Performance Improvement Prediction via Metric-Based Workload Classification by Papalekas, Dimitrios, Tziouvaras, Athanasios, Floros, George, Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…Contrary to the improvement of CPU capabilities, traditional DRAM evolution faced significant challenges that render it the main performance bottleneck in…”
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Adaptive Operation-Based ALU and FPU Clocking by Tziouvaras, Athanassios, Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…The operating clock period in modern circuits is designated under worst-case operating conditions, in order to ensure error free functionality. To accomplish…”
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Operation Dependencies in Loop Pipelining for High-Level Synthesis by Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…Research and industry interest in high-level synthesis has been renewed in the last few years, proven by the introduction of new tools or improved versions of…”
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The implementation of the flipped classroom model in the teaching of educational robotics: A study in secondary school students by Varsos, Dimitrios A., Dimitriou, Georgios, Zygouris, Nikolaos C.

“…The typical way to learn programming is using different high-level programming languages and a simple text editor, in order to compose and compile programs,…”
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Instruction-Flow-Based Timing Analysis in Pipelined Processors by Tziouvaras, Athanassios, Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock…”
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Minimal-area loop pipelining for high-level synthesis with CCC by Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level…”
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Instruction-Based Timing Analysis in Pipelined Processors by Tziouvaras, Athanassios, Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the…”
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Improved Text Emotion Prediction Using Combined Valence and Arousal Ordinal Classification by Mitsios, Michael, Vamvoukakis, Georgios, Maniati, Georgia, Ellinas, Nikolaos, Dimitriou, Georgios, Markopoulos, Konstantinos, Kakoulidis, Panos, Vioni, Alexandra, Christidou, Myrsini, Oh, Junkwang, Jho, Gunu, Hwang, Inchul, Vardaxoglou, Georgios, Chalamandaris, Aimilios, Tsiakoulis, Pirros, Raptis, Spyros

“…Emotion detection in textual data has received growing interest in recent years, as it is pivotal for developing empathetic human-computer interaction systems…”
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Loop pipelining in high-level synthesis with CCC by Dimitriou, Georgios, Dossis, Michael, Stamoulis, Georgios

“…High-level synthesis allows the use of high-level programming languages for hardware design. Traditional programming with the C and ADA languages can lead to…”
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Compiler transformations in hardware synthesis of Mpeg2 codes by Chatzianastasiou, Georgios, Tsakyridis, Apostolos, Dimitriou, Georgios, Stamoulis, Georgios, Dossis, Michael

“…High-level synthesis is the technique that translates high-level programming language programs into equivalent hardware descriptions. The use of conventional…”
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Loop scheduling for multithreaded processors by Dimitriou, Georgios

“…Loop scheduling techniques developed over the years for parallel and multiple-issue architectures may prove unsuitable for multithreaded processors. The…”
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Loop Scheduling for Multithreaded Processors by Dimitriou, G., Polychronopoulos, C.

“…The presence of multiple active threads on the same processor can mask latency by rapid context switching, but it can adversely affect performance due to…”
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