Search Results - "Diessel, Oliver"

Opportunities and challenges for dynamic FPGA reconfiguration in electronic measurement and instrumentation by Diessel, Oliver

“…Reconfigurable systems based on Field-Programmable Gate Arrays (FPGAs) can offer performance and power advantages over processor-based systems as well as cost…”
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FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs by Agiakatsikas, Dimitris, Cetin, Ediz, Diessel, Oliver

“…This paper introduces frame- and module-based configuration memory error recovery (FMER), that is, a FMER technique targeting triple modular redundant (TMR)…”
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Service-Oriented Architecture on FPGA-Based MPSoC by Chao Wang, Xi Li, Chen, Yunji, Youhui Zhang, Diessel, Oliver, Xuehai Zhou

“…The integration of software services-oriented architecture (SOA) and hardware multiprocessor system-on-chip (MPSoC) has been pursued for several years…”
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Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems by Tran Huu Nguyen, Nguyen, Cetin, Ediz, Diessel, Oliver

“…Field‐programmable gate arrays are susceptible to radiation‐induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR)…”
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Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery by Nguyen, Nguyen T.H., Agiakatsikas, Dimitris, Zhao, Zhuoran, Wu, Tong, Cetin, Ediz, Diessel, Oliver, Gong, Lingkan

“…•Reconfiguration Control Networks (RCNs) aggregate TMR voter error reports to trigger recovery from configuration memory errors in FPGA designs.•The…”
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On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs by Fan, Junning, Diessel, Oliver

“…Binarised neural networks (BNNs) have attracted research interest for embedded deep learning applications. BNNs are well suited to FPGA implementation since…”
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Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work by Wu, Tong, Diessel, Oliver

“…In the cryptocurrency mining field, algorithms have been developed to frustrate the development of ASICs that greatly out-compete general purpose hardware in…”
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Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems by Nguyen, Nguyen T. H., Cetin, Ediz, Diessel, Oliver

“…Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple…”
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Guest Editorial: Field-Programmable Technology by Shannon, Lesley, Diessel, Oliver, Bergmann, Neil W.

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Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets by Cetin, Ediz, Diessel, Oliver, Lingkan Gong

“…Field-Programmable Gate Arrays (FPGAs) provide an ideal platform for meeting the performance, cost and flexibility requirements of on-board processing in…”
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Reconfiguration network design for SEU recovery in FPGAs by Cetin, Ediz, Diessel, Oliver, Lingkan Gong, Lai, Victor

“…Field-Programmable Gate Array (FPGA) systems provide an ideal platform for meeting the computation requirements for future on-board processing. FPGAs, however,…”
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A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms by Kroh, Alexander, Diessel, Oliver

“…Due to the cost of repeated data movement between CPU and FPGA, the use of FPGA-based accelerators has traditionally been limited to offloading long-running…”
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Introduction to RAW 2019 by Lima, Fernanda, Diessel, Oliver

“…Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the…”
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Optimization of placement of dynamic network-on-chip cores using simulated annealing by Hredzak, B., Diessel, O.

“…We derive an objective function which instead of mapping/placing application task graphs in a compact manner onto reconfigurable devices, dilates the mappings…”
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A programmable multi-GNSS baseband receiver by Tran, Vinh T., Shivaramaiah, Nagaraj C., Diessel, Oliver, Dempster, Andrew G.

“…This paper assesses the drawbacks in reconfigurability and resource consumption of the conventional baseband signal processing circuitry for modern Global…”
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FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs by Agiakatsikas, Dimitris, Cetin, Ediz, Diessel, Oliver

“…High-reliability SRAM-based Field Programmable Gate Array (FPGA) designs that are deployed in space are commonly triplicated to mask Single Event Upsets (SEUs)…”
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TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS by Ganghee Lee, Agiakatsikas, Dimitris, Tong Wu, Cetin, Ediz, Diessel, Oliver

“…We present TLegUp, an extension of LegUp, that automatically generates Triple Modular Redundant designs for FPGAs from C programs. TLegUp is expected to…”
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From C to Fault-Tolerant FPGA-Based Systems by Agiakatsikas, Dimitris, Lee, Ganghee, Mitchell, Thomas, Cetin, Ediz, Diessel, Oliver

“…This work presents an automated flow for producing fault-tolerant Field Programmable Gate Array (FPGA) systems. The flow uses the TLegUp High Level Synthesis…”
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Dynamic scheduling of voter checks in FPGA-based TMR systems by Nguyen, Nguyen T. H., Agiakatsikas, Dimitris, Cetin, Ediz, Diessel, Oliver

“…SRAM-based Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring…”
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ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration by Lingkan Gong, Diessel, Oliver

“…Dynamic Partial Reconfiguration (DPR) enables software-like flexibility in hardware designs by allowing some of the logic on a Field Programmable Gate Array…”
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