Search Results - "Diaz, C. H."

An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III-V NMOS by Oxland, R., Chang, S. W., Xu Li, Wang, S. W., Radhakrishnan, G., Priyantha, W., van Dal, M. J. H., Hsieh, C. H., Vellianitis, G., Doornbos, G., Bhuwalka, K., Duriez, B., Thayne, I., Droopad, R., Passlack, M., Diaz, C. H., Sun, Y. C.

“…We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance…”
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High crystalline quality Ge grown by MOCVD inside narrow shallow trench isolation defined on Si(001) substrates by Vellianitis, G., van Dal, M.J.H., Duriez, B., Lee, T.L., Passlack, M., Wann, C.H., Diaz, C.H.

“…Narrow 〈110〉Si oriented trenches with high aspect ratio served as template to grow Ge on Si (001) substrate. Cross section high resolution transmission…”
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Development of a third-generation biosensor to determine sterigmatocystin mycotoxin: An early warning system to detect aflatoxin B1 by Díaz Nieto, C.H., Granero, A.M., Garcia, D., Nesci, A., Barros, G., Zon, M.A., Fernández, H.

“…A third-generation enzymatic biosensor was developed to quantify sterigmatocystin (STEH). It was based on a glassy carbon electrode modified with a composite…”
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An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling by Diaz, C.H., Hun-Jan Tao, Yao-Ching Ku, Yen, A., Young, K.

“…This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices…”
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Growth of heterostructures on InAs for high mobility device applications by Contreras-Guerrero, R., Wang, S., Edirisooriya, M., Priyantha, W., Rojas-Ramirez, J.S., Bhuwalka, K., Doornbos, G., Holland, M., Oxland, R., Vellianitis, G., Van Dal, M., Duriez, B., Passlack, M., Diaz, C.H., Droopad, R.

“…The growth of heterostructures lattice matched to InAs(100) substrates for high mobility electronic devices has been investigated. The oxide removal process…”
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PCM-Based Analog Compute-In-Memory: Impact of Device Non-Idealities on Inference Accuracy by Sun, X., Khwa, W. S., Chen, Y. S., Lee, C. H., Lee, H. Y., Yu, S. M., Naous, R., Wu, J. Y., Chen, T. C., Bao, X., Chang, M. F., Diaz, C. H., Wong, H.-S. P., Akarvardar, K.

“…The impact of phase change memory (PCM) device non-idealities on the deep neural network (DNN) inference accuracy is systematically investigated. Based on the…”
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Uncertainties in projected impacts of climate change on European agriculture and terrestrial ecosystems based on scenarios from regional climate models by Olesen, J. E, Carter, T. R, Díaz-Ambrona, C. H, Fronzek, S, Heidmann, T, Hickler, T, Holt, T, Minguez, M. I, Morales, P, Palutikof, J. P, Quemada, M, Ruiz-Ramos, M, Rubæk, G. H, Sau, F, Smith, B, Sykes, M. T

“…The uncertainties and sources of variation in projected impacts of climate change on agriculture and terrestrial ecosystems depend not only on the emission…”
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Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs by Chiang, H. L., Chen, T. C., Wang, J. F., Mukhopadhyay, S., Lee, W. K., Chen, C. L., Khwa, W. S., Pulicherla, B., Liao, P. J., Su, K. W., Yu, K. F., Wang, T., Wong, H. S. P., Diaz, C. H., Cai, J.

“…We present advanced FinFET characterization and circuit analysis at reduced temperatures down to 77 K. Steepened subthreshold slope enables threshold voltage…”
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High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array by Song, M. Y., Lee, C. M., Yang, S. Y., Chen, G. L., Chen, K. M., Wang, I J., Hsin, Y. C., Chang, K. T., Hsu, C. F., Li, S. H., Wei, J. H., Lee, T. Y., Chang, M. F., Bao, X. Y., Diaz, C. H., Lin, S. J.

“…We demonstrated an 8Kb SOT-MRAM array which achieves the highest field-free switching speed (1ns) never reported. The low transistor switching voltage (V SW )…”
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MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm) by Chang-Hoon Choi, Jung-Suk Goo, Tae-Young Oh, Zhiping Yu, Dutton, R.W., Bayoumi, A., Min Cao, Voorde, P.V., Vook, D., Diaz, C.H.

“…An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including…”
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Seroprevalence against R. rickettsii, R. typhi and R. felis in human samples from prioritized rural areas in department of Cauca, Colombia by Betancourt, P., Martínez-Diaz, H.-C., Mora, J. Gil, Plaza-Rojas, C., Olaya-M, L.-A., Benavides, E., Bolaños, E., Hidalgo, M.

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InAs hole inversion and bandgap interface state density of 2 × 1011 cm−2 eV−1 at HfO2/InAs interfaces by Wang, C. H., Wang, S. W., Doornbos, G., Astromskas, G., Bhuwalka, K., Contreras-Guerrero, R., Edirisooriya, M., Rojas-Ramirez, J. S., Vellianitis, G., Oxland, R., Holland, M. C., Hsieh, C. H., Ramvall, P., Lind, E., Hsu, W. C., Wernersson, L.-E., Droopad, R., Passlack, M., Diaz, C. H.

“…High-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance–voltage…”
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Pi-Gate SOI MOSFET by Jong-Tae Park, Colinge, J.-P., Diaz, C.H.

“…This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a…”
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Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices by Diaz, C.H., Sung-Mo Kang, Duvvury, C.

“…Previous work on electrothermal simulation using network analysis techniques has been of limited use due to the lack of avalanche breakdown modeling capability…”
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High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations by Wang, C. H., Doornbos, G., Astromskas, G., Vellianitis, G., Oxland, R., Holland, M. C., Huang, M. L., Lin, C. H., Hsieh, C. H., Chang, Y. S., Lee, T. L., Chen, Y. Y., Ramvall, P., Lind, E., Hsu, W. C., Wernersson, L.-E., Droopad, R., Passlack, M., Diaz, C. H.

“…Two high-k dielectric materials (Al2O3 and HfO2) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the…”
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MOVPE-grown InAs/AlAs0.16Sb0.84/InAs and InAs/AlAs0.16Sb0.84/GaSb heterostructures by Ramvall, P., Wang, C.H., Astromskas, G., Vellianitis, G., Holland, M., Droopad, R., Samuelson, L., Wernersson, L.E., Passlack, M., Diaz, C.H.

“…We demonstrate MOVPE-growth of InAs/AlAs0.16Sb0.84/GaSb and InAs/AlAs0.16Sb0.84/InAs heterostructures of excellent quality as observed by transmission electron…”
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Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design by Kleveland, B., Diaz, C.H., Vook, D., Madden, L., Lee, T.H., Wong, S.S.

“…The increasing number of interconnect layers that are needed in a CMOS process to meet the routing and power requirements of large digital circuits also yield…”
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Transistor-and Circuit-Design Optimization for Low-Power CMOS by Mi-Chang Chang, Chih-Sheng Chang, Chih-Ping Chao, Ken-Ichi Goto, Meikei Ieong, Lee-Chung Lu, Diaz, C.H.

“…CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives…”
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Short-Channel Double-Gate FETs with Atomically Precise Graphene Nanoribbons by Mutlu, Z., Lin, Y., Barin, G. B., Zhang, Z., Pitner, G., Wang, S., Darawish, R., Giovannantonio, M. Di, Wang, H., Cai, J., Passlack, M., Diaz, C. H., Narita, A., Mullen, K., Fischer, F. R., Bandaru, P., Kummel, A. C., Ruffieux, P., Fasel, R., Bokor, J.

“…High performance graphene nanoribbon (GNR) transistors require seamless integration of GNRs with high-k dielectrics, which remains unexplored. This work…”
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CMOS technology for MS/RF SoC by Diaz, C.H., Tang, D.D., Sun, J.Y.-C.

“…Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to…”
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