Search Results - "Dhilleswararao, Pudi"

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey by Dhilleswararao, Pudi, Boppu, Srinivas, Manikandan, M. Sabarimalai, Cenkeramaddi, Linga Reddy

“…In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning…”
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Automating functional unit and register binding for synchoros CGRA platform by Pudi, Dhilleswararao, Tiwari, Utsav, Boppu, Srinivas, Yang, Yu, Hemani, Ahmed

“…Coarse-grain reconfigurable architectures, which provide high computing throughput, low cost, scalability, and energy efficiency, have grown in popularity in…”
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Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework by Pudi, Dhilleswararao, Malviya, Shivam, Boppu, Srinivas, Yang, Yu, Hemani, Ahmed, Cenkeramaddi, Linga Reddy

“…Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications…”
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Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study by Pudi, Dhilleswararao, Yang, Yu, Stathis, Dimitrios, Kumar Prajapati, Sunil, Boppu, Srinivas, Hemani, Ahmed, Cenkeramaddi, Linga Reddy

“…Efficiently synthesizing an entire application that consists of multiple algorithms for hardware implementation is a very difficult and unsolved problem. One…”
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Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures by Pudi, Dhilleswararao, Ryansh, Rajeev, Goudu, Vamsi, Boppu, Srinivas, Hemani, Ahmed

“…Edge detection is a fundamental operation in image processing, serving as a crucial step in various applications such as object recognition, image…”
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Implementation of Image Averaging on DRRA and DiMArch Architectures by Pudi, Dhilleswararao, Goudu, Vamsi, Boppu, Srinivas, Ratnu, Ritika, Hemani, Ahmed

“…Image averaging is a technique used in image processing to reduce the noise present in an image. Image averaging is computationally intensive, particularly…”
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Design and Implementation of Optimized Register File for Streaming Applications by Patan, Ayazulla Khan, Stathis, Dimitrios, Dhilleswararao, Pudi, Yang, Yu, Boppu, Srinivas, Hemani, Ahmed

“…The increased demand for energy-efficient solutions compels system architects to explore the opportunities for minimizing area and power in the critical parts…”
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High SNM 32nm CNFET based 6T SRAM Cell design considering transistor ratio by Dhilleswararao, Pudi, Mahapatra, Rajat, Srinivas, P. S. T. N.

“…Carbon Nanotube Field Effect Transistor (CNFET) is best alternative to design SRAM cell in submicron range because of its excellent electrical properties, high…”
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