Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links

Network-on-Chip (NoC) has been a viable solution for resolving the complexities associated with inter-processor communications in a Chip Multi Processor (CMP). NoC accounts for a significant portion of the total power consumed by a CMP. In a standard NoC system, only a fraction of power dissipation...

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Bibliographic Details
Published in:	2021 25th International Symposium on VLSI Design and Test (VDAT) pp. 1 - 6
Main Authors:	Dev, S Sharon, Krishna, S M, Archana, S S, Kunthara, Rose George, Neethu, K, James, Rekha K
Format:	Conference Proceeding
Language:	English
Published:	IEEE 16-09-2021
Subjects:	CMP Couplings Crosstalk Encoding Heuristic algorithms low power Network-on-chip self-switching serial links Switches Very large scale integration
Online Access:	Get full text
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Summary:	Network-on-Chip (NoC) has been a viable solution for resolving the complexities associated with inter-processor communications in a Chip Multi Processor (CMP). NoC accounts for a significant portion of the total power consumed by a CMP. In a standard NoC system, only a fraction of power dissipation occurs due to static/leakage, while the rest is due to dynamic power. Dynamic dissipation includes self-switching and coupling switching dissipations, with the latter accounting for a significant part of total power dissipated. Several coding methods exist to minimize this dynamic power dissipation in NoC links. In this paper, we propose Algorithm 1 to reduce self-switching transitions and Algorithm 2 & 3 to lower coupling switching transitions in between the serial links, with Encoder/decoder modules placed at Network-Interface(NI) level. Simulations done on Xilinx Vivado design suite showed a maximum reduction of 64% in coupling switching activity compared to existing schemes.
DOI:	10.1109/VDAT53777.2021.9601003