Search Results - "Dermer, GE"

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package by Hazucha, P., Schrom, G., Jaehong Hahn, Bloechel, B.A., Hack, P., Dermer, G.E., Narendra, S., Gardner, D., Karnik, T., De, V., Borkar, S.

“…We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a…”
Get full text

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, B A, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, G E, Narendra, S, De, V, Borkar, S

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
Get full text

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS by Hoskote, Y., Bloechel, B.A., Dermer, G.E., Erraguntla, V., Finan, D., Howard, J., Klowden, D., Narendra, S.G., Ruhl, G., Tschanz, J.W., Sriram Vangal, Veeramachaneni, V., Wilson, H., Jianping Xu, Borkar, N.

“…This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This…”
Get full text

5-GHz 32-bit integer execution core in 130-nm dual-V/T/ CMOS by Vangal, S, Anders, M A, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J W, Ye, Y, Somasekhar, D, Bloechel, B A, Dermer, G E, Krishnamurthy, R K, Soumyanath, K, Mathew, S, Narendra, S G, Stan, M R

“…A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry x 2 ALU instruction scheduler loop and a 32-entry x 32-bit…”
Get full text

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, BA, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, GE, Narendra, S, De, V, Borkar, S

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
Get full text

5-GHz 32-bit integer execution core in 130-nm dual-V sub(T) CMOS by Vangal, S, Anders, MA, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J W, Ye, Y, Somasekhar, D, Bloechel, BA, Dermer, GE, Krishnamurthy, R K, Soumyanath, K, Mathew, S, Narendra, S G, Stan, M R, Thompson, S, De, V, Borkar, S

“…A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry 2 ALU instruction scheduler loop and a 32-entry 32-bit…”
Get full text

Time domain modeling of lossy interconnects by Svensson, C., Dermer, G.H.

“…A new model for dielectric loss, suitable for time domain modeling of printed circuit boards, is proposed. The model is based on a physical relaxation model…”
Get full text