Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

We present the fabrication process of a fully functional 0.274/spl mu/m2 6T-SRAM cell with inserted-Ta/sub x/N/sub y/ tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274/spl mu/m2 using fur...

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Bibliographic Details

Published in:	Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 pp. 106 - 107
Main Authors:	Witters, L., Collaert, N., Nackaerts, A., Demand, M., Demuynek, S., Delvaux, C., Lauwers, A., Baerts, C., Beckx, S., Bouilart, W., Brus, S., Degroote, B., de Marneffe, J.F., Dixit, A., De Meyer, K., Ercken, M., Goodwin, M., Hendrickx, E., Heylen, N., Jaenen, P., Laidler, D., Leray, P., Locorotondo, S., Maenhoudt, M., Moclants, M., Pollentier, I., Ronse, K., Rooyackers, R., Van Aelst, J., Vandenberghe, G., Vandeweyer, T., Vanhaelemeersch, S., Van Hove, M., Van Olmen, J., Verhaegen, S., Versluijs, J., Vrancken, C., Wiaux, V., Willems, P., Wouters, J., Jurezak, M., Biesemans, S.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2005
Subjects:	CMOS logic circuits Fabrication Instruments Layout Lighting Logic circuits Logic devices Noise reduction Random access memory Size control
Online Access:	Get full text
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