Search Results - "Demuynck, Steven"

Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction by Hao Yu, Schaekers, Marc, Schram, Tom, Rosseel, Erik, Martens, Koen, Demuynck, Steven, Horiguchi, Naoto, Barla, Kathy, Collaert, Nadine, De Meyer, Kristin, Thean, Aaron

“…Accurate determination of contact resistivities (P c ) below 1 × 10 -8 Ω · cm 2 is challenging. Among the frequently applied transmission line models (TLMs),…”
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Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO2/n-Si Contact by Hao Yu, Schaekers, Marc, Schram, Tom, Demuynck, Steven, Horiguchi, Naoto, Barla, Kathy, Collaert, Nadine, Thean, Aaron Voon-Yew, De Meyer, Kristin

“…This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height…”
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CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits by Litta, Eugenio Dentoni, Ritzenthaler, Romain, Schram, Tom, Spessot, Alessio, O Sullivan, Barry, Machkaoutsan, Vladimir, Fazan, Pierre, Ji, Yunhyuck, Mannaert, Geert, Lorant, Christophe, Sebaai, Farid, Thiam, Arame, Ercken, Monique, Demuynck, Steven, Horiguchi, Naoto

“…Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM)…”
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Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora ® LK HM by Demuynck, Steven, Huffman, Craig, Claes, Martine, Suhard, Samuel, Versluijs, Janko, Volders, Henny, Heylen, Nancy, Kellens, Kristof, Croes, Kristof, Struyf, Herbert, Vereecke, Guy, Verdonck, Patrick, Roest, David De, Beynet, Julien, Sprey, Hessel, Beyer, Gerald P.

“…Aurora ® LK HM ( k =3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora ® LK ( k =3.0) in terms…”
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Dielectric Reliability of 50nm Half Pitch Structures in Aurora® LK by Demuynck, S., Kim, H., Huffman, C., Darnon, Maxime, .Struyf, H., Versluijs, J., Claes, M., Vereecke, G., Verdonck, P., Volders, H., Heylen, N., Kellens, K., de Roest, D., Sprey, H., Beyer, G.

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Dielectric Reliability of 50 nm Half Pitch Structures in Aurora ® LK by Demuynck, Steven, Kim, Honggun, Huffman, Craig, Darnon, Maxime, Struyf, Herbert, Versluijs, Janko, Claes, Martine, Vereecke, Guy, Verdonck, Patrick, Volders, Henny, Heylen, Nancy, Kellens, Kristof, Roest, David De, Sprey, Hessel, Beyer, Gerald

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Integration of Porogen-Based Low-$k$ Films: Influence of Capping Layer Thickness and Long Thermal Anneals on Low-$k$ Damage and Reliability by Roest, David De, Vereecke, Bart, Huffman, Craig, Heylen, Nancy, Croes, Kristof, Arai, Hirofumi, Takamure, Noboru, Beynet, Julien, Sprey, Hessel, Matsushita, Kiyohiro, Kobayashi, Nobuyoshi, Verdonck, Patrick, Demuynck, Steven, Beyer, Gerald, Tokei, Zsolt, Struyf, Herbert

“…This paper discusses integration aspects of a porous low-$k$ film ($k \sim 2.45$) cured with a broadband UV lamp. Different process splits are discussed which…”
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Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle by Vincent, Benjamin, Hathwar, Raghu, Kamon, Mattan, Ervin, Joseph, Schram, Tom, Chiarella, Thomas, Demuynck, Steven, Baudot, Sylvain, Siew, Yong Kong, Kubicek, Stenfan, Litta, Eugenio Dentoni, Chew, SoonAik, Mitard, Jerome

“…A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device…”
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Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling by Gupta, Anshul, Pedreira, Olalla Varela, Arutchelvan, Goutham, Zahedmanesh, Houman, Devriendt, Katia, Mertens, Hans, Tao, Zheng, Ritzenthaler, Romain, Wang, Shouhua, Radisic, Dunja, Kenis, Karine, Teugels, Lieve, Sebai, Farid, Lorant, Christophe, Jourdan, Nicolas, Chan, Boon Teik, Subramanian, Sujith, Schleicher, Filip, Hopf, Toby, Peter, Antony Premkumar, Rassoul, Nouredine, Debruyn, Haroen, Demonie, Ingrid, Siew, Yong Kong, Chiarella, Thomas, Briggs, Basoene, Zhou, Xiuju, Rosseel, Erik, De Keersgieter, An, Capogreco, Elena, Litta, Eugenio Dentoni, Boccardi, Guillaume, Baudot, Sylvain, Mannaert, Geert, Bontemps, Noemie, Sepulveda, A., Mertens, Sofie, Kim, Min-Soo, Dupuy, Emmanuel, Vandersmissen, Kevin, Paolillo, Sara, Yakimets, Dmitry, Chehab, Bilal, Favia, Paola, Drijbooms, Christel, Cousserier, Joris, Jaysankar, Manoj, Lazzarino, Frederic, Morin, Pierre, Altamirano, Efrain, Mitard, Jerome, Wilson, Christopher J., Holsteyns, Frank, Boemmels, Juergen, Demuynck, Steven, Tokei, Zsolt, Horiguchi, Naoto

“…Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of…”
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Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes by Peter, Antony Premkumar, Tomomi, Takayama, Taishi, Ebisudani, Eiichiro, Shiba, Sepulveda, Alfonso, Blanquart, Timothee, Kimura, Yosuke, Subramanian, Sujith, Baudot, Sylvain, Basoene, Briggs, Gupta, Anshul, Veloso, Anabela, Capogreco, Elena, Mertens, Hans, Meersschaut, Johan, Conard, Thierry, Dara, Praveen, Geypen, Jef, Martinez, Gerardo, Batuk, Dmitry, Demuynck, Steven, Morin, Pierre

“…In this study, we explored the key properties and functionalities of plasma enhanced atomic layer deposition (PEALD) SiNx films, synthesized using different…”
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MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond by Hao Yu, Schaekers, Marc, Demuynck, Steven, Barla, Kathy, Mocuta, Anda, Horiguchi, Naoto, Collaert, Nadine, Thean, Aaron Voon-Yew, De Meyer, Kristin

“…Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares…”
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New methodology for modelling MOL TDDB coping with variability by Roussel, Philippe J., Chasin, Adrian, Demuynck, Steven, Horiguchi, Naoto, Linten, Dimitri, Mocuta, Anda

“…We report a novel time-dependent dielectric breakdown (TDDB) lifetime model which accounts for the impact of various sources of variability. We prove that the…”
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Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO sub(2)/n-Si Contact by Yu, Hao, Schaekers, Marc, Schram, Tom, Demuynck, Steven, Horiguchi, Naoto, Barla, Kathy, Collaert, Nadine, Thean, Aaron Voon-Yew, De Meyer, Kristin

“…This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height (…”
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Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO 2 /n-Si Contact by Yu, Hao, Schaekers, Marc, Schram, Tom, Demuynck, Steven, Horiguchi, Naoto, Barla, Kathy, Collaert, Nadine, Thean, Aaron Voon-Yew, De Meyer, Kristin

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Channel Length Dependence of PBTI in High-k First RMG Gate Stack Integration Scheme by Parihar, Narendra, Arutchelvan, Goutham, Franco, Jacopo, Baudot, Sylvain, Opedebeeck, Ann, Demuynck, Steven, Arimura, Hiroaki, Ragnarsson, Lars-Ake, Mitard, Jerome, De Heyn, Vincent, Mercha, Abdelkarim

“…The impact of channel length (L G ) scaling on the PBTI is studied on High-k First (HKF) Replacement Metal Gate (RMG) planar devices. The threshold voltage…”
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Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching 1 \times 10^ Ohm-cm2 by Hao Yu, Schaekers, Marc, Peter, Anthony, Pourtois, Geoffrey, Rosseel, Erik, Joon-Gon Lee, Woo-Bin Song, Keo Myoung Shin, Everaert, Jean-Luc, Soon Aik Chew, Demuynck, Steven, Daeyong Kim, Barla, Kathy, Mocuta, Anda, Horiguchi, Naoto, Thean, Aaron Voon-Yew, Collaert, Nadine, De Meyer, Kristin

“…In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance…”
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Full reliability study of advanced metallization options for 30 nm A12pitch interconnects by Croes, Kristof, Demuynck, Steven, Siew, Yong, Pantouvaki, Marianna, Wilson, Christopher, Heylen, Nancy, Beyer, Gerald, TAkei, Zsolt

“…Different metallization options that allow filling 30 nm A12pitch interconnect trenches have been explored and their full reliability performance has been…”
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Full reliability study of advanced metallization options for 30nm ½pitch interconnects by Croes, Kristof, Demuynck, Steven, Siew, Yong Kong, Pantouvaki, Marianna, Wilson, Christopher J., Heylen, Nancy, Beyer, Gerald P., Tőkei, Zsolt

“…Different metallization options that allow filling 30nm ½pitch interconnect trenches have been explored and their full reliability performance has been…”
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Reliability of MOL local interconnects by Kauerauf, T., Branka, A., Sorrentino, G., Roussel, P., Demuynck, S., Croes, K., Mercha, K., Bommels, J., Tokei, Z., Groeseneken, G.

“…From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and…”
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Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances by NOORI, Atif M, BALSEANU, Mihaela, LAUWERS, Anne, LEE, Wen-Chin, JIANXIN LEI, MANDREKAR, Tushar, SCHREUTELKAMP, Robert, SHAH, Kavita, THOMPSON, Scott E, VERHEYEN, Peter, WANG, Ching-Ya, XIA, Li-Qun, BOELEN, Pieter, ARGHAVANI, Reza, COCKBUM, Andrew, DEMUYNCK, Steven, FELCH, Susan, GANDIKOTA, Srinivas, JERRY GELATOS, A, KHANDELWAL, Amit, KITTL, Jorge A

“…Manufacturable processes to reduce both channel and external resistances (R@@dExt@) in CMOS devices are described. Simulations show that R@@dExt@ will become…”
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