Search Results - "Deloffre, E."

Contact Resistivity of Submicron Hybrid Bonding Pads Down to 400 nm by Lhostis, S., Ayoub, B., Sart, C., Moreau, S., Souchier, E., Gusmao Cacho, M. G., Deloffre, E., Mermoz, S., Rey, C., Le Roux, F., Aybeke, E., Gallois-Garreignot, S., Frémont, H., Tournier, A.

“…Three-dimensional (3D) stacking using hybrid bonding is the most scalable method for 3D integration. As the hybrid bonding pad width is reduced to adopt a…”
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FDSOI devices with thin BOX and ground plane integration for 32 nm node and below by Fenouillet-Beranger, C., Denorme, S., Perreau, P., Buj, C., Faynot, O., Andrieu, F., Tosti, L., Barnola, S., Salvetat, T., Garros, X., Cassé, M., Allain, F., Loubet, N., Pham-Nguyen, L., Deloffre, E., Gros-Jean, M., Beneyton, R., Laviron, C., Marin, M., Leyris, C., Haendler, S., Leverd, F., Gouraud, P., Scheiblin, P., Clement, L., Pantel, R., Deleonibus, S., Skotnicki, T.

“…In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX (Buried Oxide) thicknesses with or without ground plane (GP). With a simple…”
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Electrical properties in low temperature range (5 K–300 K) of Tantalum Oxide dielectric MIM capacitors by Deloffre, E., Montès, L., Ghibaudo, G., Bruyère, S., Blonkowski, S., Bécu, S., Gros-Jean, M., Crémer, S.

“…Tantalum oxide (Ta 2O 5) is widely used for MIM (Metal-Insulator-Metal) capacitor owing of its high dielectric constant. This work examines current–voltage and…”
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Integration of a high density Ta2O5 MIM capacitor following 3D damascene architecture compatible with copper interconnects by THOMAS, M, FARCY, A, DELOFFRE, E, CREMER, S, BRUYERE, S, CHENEVIER, B, TORRES, J, GAILLARD, N, PERROT, C, GROS-JEAN, M, MATKO, I, CORDEAU, M, SAIKALY, W, PROUST, M, CAUBET, P

“…To face with the continuous integrated circuit densification, passive components size has to be reduced, particularly for RF and analog applications where lots…”
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Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution by Bidal, G., Loubet, N., Fenouillet-Beranger, C., Denorme, S., Perreau, P., Fleury, D., Clement, L., Laviron, C., Leverd, F., Gouraud, P., Barnola, S., Beneyton, R., Torres, A., Duluard, C., Chapon, J.D., Orlando, B., Salvetat, T., Grosjean, M., Deloffre, E., Pantel, R., Dutartre, D., Monfray, S., Ghibaudo, G., Boeuf, F., Skotnicki, T.

“…This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance…”
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High-Performance High- K/Metal Planar Self-Aligned Gate-All-Around CMOS Devices by Pouydebasque, A., Denorme, S., Loubet, N., Wacquez, R., Bustos, J., Leverd, F., Deloffre, E., Barnola, S., Dutartre, D., Coronel, P., Skotnicki, T.

“…By introducing high- K dielectrics and metal gate in our planar self-aligned gate-all-around (GAA) fabrication process, we have successfully fabricated sub-35…”
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Reliable 300 mm Wafer Level Hybrid Bonding for 3D Stacked CMOS Image Sensors by Lhostis, S., Farcy, A., Deloffre, E., Lorut, F., Mermoz, S., Henrion, Y., Berthier, L., Bailly, F., Scevola, D., Guyader, F., Gigon, F., Besset, C., Pellissier, S., Gay, L., Hotellier, N., Le Berrigo, A.-L, Moreau, S., Balan, V., Fournel, F., Jouve, A., Cheramy, S., Arnoux, M., Rebhan, B., Maier, G. A., Chitu, L.

“…3D Stacked Image sensor is the stacking of a Back-Side Illuminated (BSI) CMOS Image Sensor on a logic die. It enables compact size, higher performances and…”
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Impact of Process Variations on the Capacitance and Electrical Resistance down to 1.44\ \mu\mathrm Hybrid Bonding Interconnects by Ayoub, B., Lhostis, S., Moreau, S., Perez, E. Leon, Jourdon, J., Lamontagne, P., Deloffre, E., Mermoz, S., de Buttet, C., Balan, V., Euvard, C., Exbrayat, Y., Fremont, H.

“…With the rising of Hybrid Bonding (HB) as an interesting solution for fine-pitch 3D integration, the influence of process induced variations on performances is…”
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Stability of capacitance voltage linearity for high-k MIM capacitor by Besset, C., Bruyere, S., Monsieur, F., Boret, S., Deloffre, E., Vincent, E.

“…The need for increased MIM capacitance density has led to the introduction of new high-k dielectric materials into both CMOS and BiCMOS technologies. These…”
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High density chip-to-wafer integration using self-assembly: On the performances of directly interconnected structures made by direct copper/oxyde bonding by Mermoz, S., Sanchez, L., Di Cioccio, L., Berthier, J., Deloffre, E., Coudrain, P., Fretigny, C.

“…We present here our latest results on chips-to-wafer 3D structures obtained with the self-assembly technology adapted on copper/oxide patterned surfaces…”
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200 nm Wafer-to-wafer overlay accuracy in wafer level Cu/SiO2 hybrid bonding for BSI CIS by Rebhan, B., Bernauer, M., Wagenleitner, T., Heilig, M., Kurz, F., Lhostis, S., Deloffre, E., Jouve, A., Balan, V., Chitu, L.

“…Sub 200 nm wafer-to-wafer (w2w) overlay accuracy on the entire 300 mm wafer was successfully demonstrated via wafer level Cu/SiO 2 hybrid bonding. Cu bonding…”
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New challenges and opportunities for 3D integrations by Michailos, J., Coudrain, P., Farcy, A., Hotellier, N., Cheramy, S., Lhostis, S., Deloffre, E., Sanchez, Y., Jouve, A., Guyader, F., Saugier, E., Fiori, V., Vivet, P., Vinet, M., Fenouillet-Beranger, C., Casset, F., Batude, P., Breuf, F., Henrion, Y., Vianne, B., Collin, L.-M, Colonna, J.-P, Benaissa, L., Brunet, L., Prieto, R., Velard, R., Ponthenier, F.

“…From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of…”
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Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability by Arnaud, L., Moreau, S., Jouve, A., Jani, I., Lattard, D., Fournel, F., Euvrard, C., Exbrayat, Y., Balan, V., Bresson, N., Lhostis, S., Jourdon, J., Deloffre, E., Guillaumet, S., Farcy, A., Gousseau, S., Arnoux, M.

“…This paper presents the description of direct hybrid bonding technology for the fabrication of vertical interconnects thanks to wafer-to-wafer bonding. Process…”
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Use of optical metrology for wafer level packaging of CMOS image sensor by Le Cunff, D, Pravdivtsev, A, Le Chao, K, Couvrat, S, Euvrard, C, Deloffre, E, Cailean, A

“…For WLP and 3D integration, wafers are processed through several steps which generally include bounding and thinning processes. Those processes are generally…”
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Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness by Jourdon, J., Lhostis, S., Moreau, S., Chossat, J., Arnoux, M., Sart, C., Henrion, Y., Lamontagne, P., Arnaud, L., Bresson, N., Balan, V., Euvrard, C., Exbrayat, Y., Scevola, D., Deloffre, E., Mermoz, S., Martin, A., Bilgen, H., Andre, F., Charles, C., Bouchu, D., Farcy, A., Guillaumet, S., Jouve, A., Fremont, H., Cheramy, S.

“…Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A…”
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High-Performance High-[Formula Omitted]/Metal Planar Self-Aligned Gate-All-Around CMOS Devices by Pouydebasque, A, Denorme, S, Loubet, N, Wacquez, R, Bustos, J, Leverd, F, Deloffre, E, Barnola, S, Dutartre, D, Coronel, P, Skotnicki, T

“…By introducing high-K dielectrics and metal gate in our planar self-aligned gate-all-around (GAA) fabrication process, we have successfully fabricated sub-35…”
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FDSOI devices with thin BOX and ground plane integration for 32nm node and below by Fenouillet-Beranger, C., Denorme, S., Perreau, P., Buj, C., Faynot, O., Andrieu, F., Tosti, L., Barnola, S., Salvetat, T., Garros, X., Cassé, M., Allain, F., Loubet, N., Pham-Nguyen, L., Deloffre, E., Gros-Jean, M., Beneyton, R., Laviron, C., Marin, M., Leyris, C., Haendler, S., Leverd, F., Gouraud, P., Scheiblin, P., Clement, L., Pantel, R., Deleonibus, S., Skotnicki, T.

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FDSOI devices with thin BOX and ground plane integration for 32nm node and below by Fenouillet-Beranger, C., Denorme, S., Perreau, P., Buj, C., Faynot, O., Andrieu, F., Tosti, L., Barnola, S., Salvetat, T., Garros, X., Casse, M., Allain, F., Loubet, N., Pham-NGuyen, L., Deloffre, E., Gros-Jean, M., Beneyton, R., Laviron, C., Marin, M., Leyris, C., Haendler, S., Leverd, F., Gouraud, P., Scheiblin, P., Clement, L., Pantel, R., Deleonibus, S., Skotnicki, T.

“…In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate…”
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Integration of a high density Ta 2O 5 MIM capacitor following 3D damascene architecture compatible with copper interconnects by Thomas, M., Farcy, A., Gaillard, N., Perrot, C., Gros-Jean, M., Matko, I., Cordeau, M., Saikaly, W., Proust, M., Caubet, P., Deloffre, E., Crémer, S., Bruyère, S., Chenevier, B., Torres, J.

“…To face with the continuous integrated circuit densification, passive components size has to be reduced, particularly for RF and analog applications where lots…”
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Atomic Layer Deposition: An Enabling Technology for Microelectronic Device Manufacturing by Fourmun Lee, Marcus, S., Shero, E., Wilk, G., Swerts, J., Maes, J.W., Blomberg, T., Delabie, A., Gros-Jean, M., Deloffre, E.

“…Atomic layer deposition (ALD) recently emerged as an enabling technology for microelectronic device fabrication. This technique provides the unique capability…”
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