Search Results - "Delie, Gilles"

Variability of band alignment between WS2 and SiO2: Intrinsic versus extrinsic contributions by Delie, Gilles, Litwin, Peter M., Abad, Gaby C., McDonnell, Stephen J., Chiappe, Daniele, Afanasiev, Valeri V.

“…Internal photoemission of electrons was used to determine the energy position of the top valence band of mono- and few-layer WS2 on an SiO2/Si substrate. It…”
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Future materials for beyond Si integrated circuits: a Perspective by Colombo, Luigi, Kazzi, Salim El, Popovici, Mihaela, Delie, Gilles, Kwon, Dae Seon, McMitchell, Sean RC, Adelmann, Christoph

“…The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later,…”
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Redefining 2-Level Semi-Damascene Interconnect Technology: Benchmarking three different Fully Self-aligned Via options by Marti, Giulio, Delie, Gilles, Murdoch, Gayle, Gupta, Anshul, Kundu, Souvik, Decoster, Stefan, Pedreira, Olalla Varela, Lesniewska, Alicja, Hermans, Yanick, Kenens, Bart, Okudur, Fulya Ulu, Park, Seongho, Tokei, Zsolt

“…This study highlights the effectiveness of a novel two-metal-level semi-damascene integration approach using fully self-aligned pillar-vias (FSAV) for…”
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Airgap Integration in MP18 Two-Level Semi-damascene Interconnects with Fully Self-aligned Vias by Delie, Gilles, Murdoch, Gayle, Marti, Giulio, Gupta, Anshul, Wu, Chen, Lesniewska, Alicja, Gavrilov, Anton, Ciofi, Ivan, Kundu, Souvik, Decoster, Stefan, Park, Seongho, Tokei, Zsolt

“…Airgap integration in 18 to 26 nm metal pitch (MP) two-metal level semi-damascene interconnects with fully self-aligned vias (FSAV) on 300 mm wafers is…”
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Selecting Alternative Metals for Advanced Interconnects by Soulié, Jean-Philippe, Sankaran, Kiroubanand, Van Troeye, Benoit, Leśniewska, Alicja, Pedreira, Olalla Varela, Oprins, Herman, Delie, Gilles, Fleischmann, Claudia, Boakes, Lizzie, Rolin, Cédric, Ragnarsson, Lars-Åke, Croes, Kristof, Park, Seongho, Swerts, Johan, Pourtois, Geoffrey, Tőkei, Zsolt, Adelmann, Christoph

“…Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor…”
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Demonstration of MP18-26nm Ru Semi-Damascene Spacer-is-Dielectric SADP Integration by Wu, Chen, Decoster, Stefan, Renaud, Vincent, Hermans, Yannick, Marien, Philippe, Marti, Giulio, Heylen, Nancy, Kenens, Bart, Roy, Syamashree, Okudur, Fulya Ulu, Le, Quoc Toan, Reddy, Naveen, Marquez, Alfonso Sepulveda, Delie, Gilles, Gupta, Anshul, Lesniewska, Alicja, Murdoch, Gayle, Park, Seongho, Tokei, Zsolt

“…This work presents a novel Spacer-is-Dielectric (SID) SADP Ru semi-damascene integration scheme by using metal-based core and gap hard masks. More than 70%…”
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Two-level Semi-damascene interconnect with fully self-aligned Vias at MP18 by Marti, Giulio, Pokhrel, Ankit, Murdoch, Gayle, Delie, Gilles, Gupta, Anshul, Marien, Philippe, Lesniewska, Alicja, Decoster, Stefan, Kundu, Souvik, Le, Quoc Toan, Oniki, Yusuke, Kenens, Bart, Hermans, Yanick, Park, Seongho, Tokei, Zsolt

“…We present the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects varying 26 to 18nm metal pitch, using…”
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Two-metal-level semi-damascene interconnect at metal pitch 18 nm and aspect-ratio 6 routed using fully self-aligned via by Gupta, Anshul, Marti, Giulio, Delie, Gilles, Kundu, Souvik, Decoster, Stefan, Pedreira, Olalla Varela, Kenens, Bart, Farokhnejad, Anita, Hermans, Yannick, Wachter, Bart de, Gavrilov, Anton, Lesniewska, Alicja, Oniki, Yusuke, Pacco, Antoine, Murdoch, Gayle, Park, Seongho, Tokei, Zsolt

“…High-aspect ratio (HAR-6-8) bottom Ru metal lines (M2), at CDs 7-10 nm and metal pitch (MP) 18-26 nm, in a two-metal level Ru semi-damascene interconnect…”
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