Search Results - "Dechamp, J."

Temporary polymer bonding for the manufacturing of thin wafers: An innovative low temperature process by Montméat, P., Bally, L., Dechamp, J., Enot, T., Fournel, F.

“…The study deals with the handling of thin wafers in 3D integration. It concerns the fabrication of 300 mm wafers in industrial tools. Usually, the…”
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Silicon-On-Diamond layer integration by wafer bonding technology by Rabarot, M., Widiez, J., Saada, S., Mazellier, J.-P., Lecouvey, C., Roussin, J.-C., Dechamp, J., Bergonzo, P., Andrieu, F., Faynot, O., Deleonibus, S., Clavelier, L., Roger, J.P.

“…In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI)…”
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Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut™ technology by Widiez, J., Rabarot, M., Saada, S., Mazellier, J.-P., Dechamp, J., Delaye, V., Roussin, J.-C., Andrieu, F., Faynot, O., Deleonibus, S., Bergonzo, P., Clavelier, L.

“…In this paper, Silicon on Diamond (SOD) substrates were fabricated using the direct bonding process in two different technologies: the BESOI (Bonded and…”
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Chip-to-chip interconnections based on the wireless capacitive coupling for 3D integration by Charlet, B., Di Cioccio, L., Dechamp, J., Zussy, M., Enot, T., Canegallo, R., Fazzi, A., Guerrieri, R., Magagni, L.

“…Chip-to-chip interconnection, based on wireless communication by capacitive coupling was investigated. This innovative approach will considerably reduce the…”
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First demonstration of heat dissipation improvement in CMOS technology using Silicon-On-Diamond (SOD) substrates by Mazellier, J.-P., Widiez, J., Andrieu, F., Lions, M., Saada, S., Hasegawa, M., Tsugawa, K., Brevard, L., Dechamp, J., Rabarot, M., Delaye, V., Cristoloveanu, S., Clavelier, L., Deleonibus, S., Bergonzo, P., Faynot, O.

“…We have fabricated Silicon-On-Diamond (SOD) substrates on which, for the first time, we integrated n and p Fully Depleted MOSFETs high-K/metal gate down to…”
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Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development by Bourjot, E., Stewart, P., Dubarry, C., Lagoutte, E., Rolland, E., Bresson, N., Romano, G., Scevola, D., Balan, V., Dechamp, J., Zussy, M., Mauguen, G., Castan, C., Sanchez, L., Jouve, A., Fournel, F., Cheramy, S.

“…Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches…”
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Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement by Jouve, A., Sinquin, Y., Garnier, A., Daval, M., Chausse, P., Argoud, M., Allouti, N., Baud, L., Dechamp, J., Franiatte, R., Cheramy, S., Kato, H., Kondo, K.

“…This paper is dedicated to the full integration of innovative silicon-based material for Wafer-Level molding of silicon interposer wafers. This technology can…”
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Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking by Radu, I, Landru, D, Gaudin, G, Riou, G, Tempesta, C, Letertre, F, Di Cioccio, L, Gueguen, P, Signamarcheix, T, Euvrard, C, Dechamp, J, Clavelier, L, Sadaka, M

“…This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer…”
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Origin of the TTV of thin films obtained by temporary bonding ZoneBond® technology by Montméat, P., Enot, T., Pellat, M., Fournel, F., Bally, L., Baud, L., Dechamp, J., Eleouet, R., Vignoud, L., Zussy, M.

“…This paper deals with the improvement of the TTV values (Total Thickness Variation) of 300 mm silicon wafers thinned down at 100 μm using the ZoneBond ®…”
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Direct bonding of titanium layers on silicon by Baudin, F., Di Cioccio, L., Delaye, V., Chevalier, N., Dechamp, J., Moriceau, H., Martinez, E., Bréchet, Y.

“…Direct metal bonding is a key technology for 3D integration that will allow semiconductor industry to go beyond predicted problems of future ICs. In this…”
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High piezoelectric properties in LiNbO3 transferred layer by the Smart Cut™ technology for ultra wide band BAW filter applications by Moulet, J.-S., Pijolat, M., Dechamp, J., Mazen, F., Tauzin, A., Rieutord, F., Reinhardt, A., Defay, E., Deguet, C., Ghyselen, B., Clavelier, L., Aid, M., Ballandras, S., Mazure, C.

“…For the first time, high overtone bulk acoustic resonators (HBAR) based on thin homogeneous and single crystalline films (below 1mum) of lithium niobate (LiNbO…”
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Direct bonding of titanium layers on silicon : WaferBond'11, International Conference on Wafer Bonding for Microsystems, 3D- and Wafer Level Integration by BAUDIN, F, DI CIOCCIO, L, DELAYE, V, CHEVALIER, N, DECHAMP, J, MORICEAU, H, MARTINEZ, E, BRECHET, Y

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Herbal medicinal products and patients' needs in Europe by DECHAMP, J.-F

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Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut™ technology: Selected Full-Length Extended Papers from the EUROSOI 2009 Conference by WIDIEZ, J, RABAROT, M, BERGONZO, P, CLAVELIER, L, SAADA, S, MAZELLIER, J.-P, DECHAMP, J, DELAYE, V, ROUSSIN, J.-C, ANDRIEU, F, FAYNOT, O, DELEONIBUS, S

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Germanium-on-insulator (GeOI) structures realized by the Smart Cut/spl trade/ technology by Deguet, C., Morales, C., Dechamp, J., Hartmann, J.M., Charvet, A.M., Moriceau, H., Chieux, F., Beaumont, A., Clavelier, L., Loup, V., Kernevez, N., Raskin, G., Richtarch, C., Allibert, F., Letertre, F., Mazure, C.

“…This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using the smart cut technology, in the preparation of the donor…”
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Ultra-thin buried nitride integration for multi-VT, low-variability and power management in planar FDSOI CMOSFETs by Nguyen, P., Andrieu, F., Garros, X., Widiez, J., Molas, G., Tisseur, R., Weber, O., Toffoli, A., Allain, F., Lafond, D., Dansas, H., Tabone, C., Brevard, L., Dechamp, J., Guiot, E., Faynot, O.

“…We highlight an original solution to adjust the threshold voltage (V T ) of Fully Depleted Silicon-On-Insulator CMOS down to L=20nm gate length thanks to…”
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Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration by Taibi, R., Di Cioccio, L., Chappaz, C., Francou, M., Dechamp, J., Larre, P., Moreau, S., Chapelon, L.-L, Fortunier, R.

“…We investigate for the first time the reliability of the direct copper bonding process. Electromigration (EM) and Stress Induced Voiding (SIV) tests are…”
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Challenges and solutions for ultra-thin (50 μm) silicon using innovative ZoneBOND™ process by Vial, K., Jouve, A., Rolland, E., Coudrain, P., Aumont, C., Foumel, F., Pellat, M., Montmeat, P., Allouti, N., Eleouet, R., Argoud, M., Dechamp, J., Bally, L., Vignoud, L., Hida, R., Ratin, C., Magis, T., Loup, V., Kachtouli, R., Gabette, L., Mourier, T., Laviron, C., Cheramy, S., Sillon, N.

“…The purpose of this paper is to investigate integration results of 300mm silicon wafers thinned at 80μm down to 50μm using the innovative temporary ZoneBOND™…”
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WSS and ZoneBOND temporary bonding techniques comparison for 80μm and 55μm functional interposer creation by Jouve, A., Vial, K., Rolland, E., Coudrain, P., Aumont, C., Laviron, C., Fournel, F., Pellat, M., Montmeat, P., Allouti, N., Eleouet, R., Argoud, M., Dechamp, J., Bally, L., Vignoud, L., Donche, C., Hida, R., Ratin, C., Magis, T., Loup, V., Kachtouli, R., Gabette, L., Mourier, T., Cheramy, S., Sillon, N.

“…Three-dimensional (3D) stacked IC technologies have become a central topic over the past few years, and start to become reality with the introduction of 3D…”
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An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling by Di Cioccio, L., Gueguen, P., Taibi, R., Signamarcheix, T., Bally, L., Vandroux, L., Zussy, M., Verrun, S., Dechamp, J., Leduc, P., Assous, M., Bouchu, D., de Crecy, F., Chapelon, L.-L., Clavelier, L.

“…An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or…”
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