Search Results - "DeBord, Jeffrey R. D"

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    Yield Learning and Process Optimization on 65-nm CMOS Technology Accelerated by the Use of Short Flow Test Die by DeBord, J.R.D., Sridhar, N.

    “…Short loop test flows have been commonly used in back-end-of-line (BEOL) interconnect process development to speed up learning rates and improve yields. This…”
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    Journal Article Conference Proceeding
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    Failure Mode Detection and Process Optimization for 65 nm CMOS Technology by DeBord, J.R.D., Olsen, L., Jin Zhao, Bonifield, T., Lytle, S.

    “…Short loop test flows have been commonly used in back end of line (BEOL) interconnect process development to speed up learning rates and improve yields. This…”
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    Conference Proceeding
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