Search Results - "Das, Tejasvi"

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  1. 1

    A High-Efficiency Capacitor-Less LDO with Adaptive Dynamic Range Extension for Biosensing Applications by Wright, Will, Das, Tejasvi

    “…This paper introduces an on-chip capacitor-less Low Dropout Regulator (LDO) with dynamic range extension that targets low-power biosensing applications. A…”
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    Conference Proceeding
  2. 2

    Throughput Optimization for Time-Domain Neuromorphic Computing by Bergthold, Karsten, Hendy, Hagar, Merkel, Cory, Das, Tejasvi

    “…We present a low-power, low-area delay cell topology for time-domain (TD) neuromorphic computing. Each cell computes partial dot product operations using…”
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    Conference Proceeding
  3. 3

    Design Space Exploration of Memristor-based Delay Cells for Time-domain Neuromorphic Computing by Hendy, Hagar, Bergthold, Karsten, Das, Tejasvi, Merkel, Cory

    “…We present a memristor-based delay cell design for time-domain neuromorphic computing inference. Each cell computes partial dot product operations using…”
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    Conference Proceeding
  4. 4

    An Analog Payload Trojan via Power-Supply Harmonic Coupling in Front-End Circuits by Ranganatham, Ramana, Das, Tejasvi

    “…The increase in number of secure systems that rely on integrated circuits (ICs) to perform their functions has exponentially risen over the past several years…”
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    Conference Proceeding
  5. 5

    Self-calibration of input-match in RF front-end circuitry by Das, T., Gopalan, A., Washburn, C., Mukund, P.R.

    “…The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed…”
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    Journal Article
  6. 6

    Towards Fault-Tolerant RF Front Ends by Das, Tejasvi, Gopalan, Anand, Washburn, Clyde, Mukund, P R

    Published in Journal of electronic testing (01-12-2006)
    “…The continuing trends of scaling have brought with them an ever-increasing array of process faults and fabrication complexities. The relentless march towards…”
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    Journal Article
  7. 7

    Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry by Das, T., Mukund, P.R.

    “…RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration…”
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    Conference Proceeding
  8. 8

    Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry by Das, Tejasvi, Mukund, P. R.

    “…RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration…”
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    Conference Proceeding
  9. 9

    Self-calibration of gain and output match in LNAs by Das, T., Mukund, P.R.

    “…Increasing process variations and tolerance limits with successive scaling, along with rising costs per design cycle have made the fault-tolerance paradigm…”
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    Conference Proceeding
  10. 10

    An ultra-fast, on-chip BiST for RF low noise amplifiers by Gopalan, A., Das, T., Washburn, C., Mukund, P.R.

    “…This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low…”
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    Conference Proceeding
  11. 11

    Impact of asymmetric metal coverage on high performance MOSFET mismatch by Fukumoto, Jay, Das, Tejasvi, Paradis, Ken, Burleson, Jeff, Moon, J.E., Mukund, P.R.

    Published in Solid-state electronics (01-10-2004)
    “…Device mismatch is responsible for significant performance degradation of integrated RF transceivers and differential circuits in digital systems…”
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    Journal Article
  12. 12

    Use of source degeneration for non-intrusive BIST of RF front-end circuits by Gopalan, A., Das, T., Washbum, C., Mukund, P.R.

    “…This paper presents an on-chip BIST technique for a common class of RF communication circuits, which has no measurable impact on the performance of the…”
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    Conference Proceeding
  13. 13

    Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs by Das, T., Washburn, C., Mukund, P.R., Howard, S., Paradis, K., Jung-Geau Jang, Kolnik, J., Burleson, J.

    “…In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFET's at GHz frequencies. We study the…”
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    Conference Proceeding
  14. 14

    Dynamic input match correction in RF low noise amplifiers by Das, T., Gopalan, A., Washburn, C., Mukund, P.R.

    “…The input match of low noise amplifiers can degrade significantly due to process faults and the parasitic package inductances at its input pad. These…”
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    Conference Proceeding
  15. 15

    A low noise current-mode readout circuit for CMOS image sensing applications by Das, T., Mukund, P.R.

    “…A major obstacle in current-mode CMOS image sensors is the transconductance gain mismatch across pixels, which translates to Fixed Pattern Noise (FPN),…”
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    Conference Proceeding
  16. 16

    A generic macromodel for coupling between inductors and interconnects for R.F.I.C. layouts by Das, T., Nayak, G., Mukund, P.R.

    “…A process independent model for calculating the electromagnetic coupling between inductors and interconnects in CMOS technology is presented. This model is…”
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    Conference Proceeding
  17. 17

    Impact of asymmetric metal coverage on high performance MOSFET mismatch by Fukumoto, J., Burleson, J., Das, T., Moon, J.E., Mukund, P.R.

    “…This paper presents a comprehensive study of the impact of asymmetric metal coverage on matched high performance MOSFET pairs for applications. Test structures…”
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    Conference Proceeding
  18. 18

    DREAM: a chip-package co-design tool for RF-mixed signal systems by Nayak, G., Das, T., Rao, T.M., Mukund, P.R.

    “…'Package aware' IC design has not only become advantageous, but also essential towards optimum performance of high-end systems. Here, an early design tool has…”
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    Conference Proceeding