Search Results - "Das, Tejasvi"
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1
A High-Efficiency Capacitor-Less LDO with Adaptive Dynamic Range Extension for Biosensing Applications
Published in 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS) (11-08-2024)“…This paper introduces an on-chip capacitor-less Low Dropout Regulator (LDO) with dynamic range extension that targets low-power biosensing applications. A…”
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2
Throughput Optimization for Time-Domain Neuromorphic Computing
Published in 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS) (11-08-2024)“…We present a low-power, low-area delay cell topology for time-domain (TD) neuromorphic computing. Each cell computes partial dot product operations using…”
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3
Design Space Exploration of Memristor-based Delay Cells for Time-domain Neuromorphic Computing
Published in 2024 IEEE International Symposium on Circuits and Systems (ISCAS) (19-05-2024)“…We present a memristor-based delay cell design for time-domain neuromorphic computing inference. Each cell computes partial dot product operations using…”
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4
An Analog Payload Trojan via Power-Supply Harmonic Coupling in Front-End Circuits
Published in 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS) (16-06-2024)“…The increase in number of secure systems that rely on integrated circuits (ICs) to perform their functions has exponentially risen over the past several years…”
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5
Self-calibration of input-match in RF front-end circuitry
Published in IEEE transactions on circuits and systems. II, Express briefs (01-12-2005)“…The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed…”
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Journal Article -
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Towards Fault-Tolerant RF Front Ends
Published in Journal of electronic testing (01-12-2006)“…The continuing trends of scaling have brought with them an ever-increasing array of process faults and fabrication complexities. The relentless march towards…”
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Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry
Published in 2007 Design, Automation & Test in Europe Conference & Exhibition (01-04-2007)“…RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration…”
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8
Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 16-20 Apr. 2007 (16-04-2007)“…RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration…”
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9
Self-calibration of gain and output match in LNAs
Published in 2006 IEEE International Symposium on Circuits and Systems (ISCAS) (2006)“…Increasing process variations and tolerance limits with successive scaling, along with rising costs per design cycle have made the fault-tolerance paradigm…”
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10
An ultra-fast, on-chip BiST for RF low noise amplifiers
Published in 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (2005)“…This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low…”
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11
Impact of asymmetric metal coverage on high performance MOSFET mismatch
Published in Solid-state electronics (01-10-2004)“…Device mismatch is responsible for significant performance degradation of integrated RF transceivers and differential circuits in digital systems…”
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12
Use of source degeneration for non-intrusive BIST of RF front-end circuits
Published in 2005 IEEE International Symposium on Circuits and Systems (ISCAS) (2005)“…This paper presents an on-chip BIST technique for a common class of RF communication circuits, which has no measurable impact on the performance of the…”
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13
Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs
Published in 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (2005)“…In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFET's at GHz frequencies. We study the…”
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14
Dynamic input match correction in RF low noise amplifiers
Published in 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings (2004)“…The input match of low noise amplifiers can degrade significantly due to process faults and the parasitic package inductances at its input pad. These…”
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15
A low noise current-mode readout circuit for CMOS image sensing applications
Published in 17th International Conference on VLSI Design. Proceedings (2004)“…A major obstacle in current-mode CMOS image sensors is the transconductance gain mismatch across pixels, which translates to Fixed Pattern Noise (FPN),…”
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16
A generic macromodel for coupling between inductors and interconnects for R.F.I.C. layouts
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…A process independent model for calculating the electromagnetic coupling between inductors and interconnects in CMOS technology is presented. This model is…”
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17
Impact of asymmetric metal coverage on high performance MOSFET mismatch
Published in International Semiconductor Device Research Symposium, 2003 (2003)“…This paper presents a comprehensive study of the impact of asymmetric metal coverage on matched high performance MOSFET pairs for applications. Test structures…”
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18
DREAM: a chip-package co-design tool for RF-mixed signal systems
Published in IEEE Computer Society Annual Symposium on VLSI (2004)“…'Package aware' IC design has not only become advantageous, but also essential towards optimum performance of high-end systems. Here, an early design tool has…”
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