Search Results - "Dartu, F."

Weibull-based analytical waveform model by Amin, C.S., Dartu, F., Ismail, Y.I.

“…Current complimentary metal-oxide-semiconductor technologies are characterized by interconnect lines with increased relative resistance with respect to driver…”
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Performance computation for precharacterized CMOS gates with RC loads by Dartu, F., Menezes, N., Pileggi, L.T.

“…For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are…”
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Statistical gate delay model considering multiple input switching by Agarwal, Aseem, Dartu, Florentin, Blaauw, David

“…There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent…”
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Statistical static timing analysis: how simple can we get? by Amin, Chirayu S., Menezes, Noel, Killpack, Kip, Dartu, Florentin, Choudhury, Umakanta, Hakim, Nagib, Ismail, Yehea I.

“…With an increasing trend in the variation of the primary parameters affecting circuit performance, the need for statistical static timing analysis (SSTA) has…”
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TETA: transistor-level waveform evaluation for timing analysis by Acar, E., Dartu, F., Pileggi, L.T.

“…Static timing analysis breaks down the longest path problem into waveform analysis of paths of logic stages that are comprised of nonlinear transistors and…”
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CMOS gate delay models for general RLC loading by Arunachalam, R., Dartu, F., Pileggi, L.T.

“…Gate and cell level timing analysis remains popular yet inherently incompatible with RC and RCL interconnect loads. The Ceff concept was proposed in Qian et…”
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An explicit RC-circuit delay approximation based on the first three moments of the impulse response by Tutuianu, B., Dartu, F., Pileggi, L.

“…Due to its simplicity, the ubiquitous Elmore delay, or first moment of the impulse response, has been an extremely popular delay metric for analyzing RC trees…”
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Piece-wise approximations of RLCK circuit responses using moment matching by Amin, Chirayu S., Ismail, Yehea I., Dartu, Florentin

“…Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC…”
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A gate-delay model for high-speed CMOS circuits by Dartu, Florentin, Menezes, Noel, Qian, Jessica, Pillage, Lawrence T.

“…As signal speeds increase and gate delays decrease for high-performance digital integrated circuits, the gate delay modeling problem becomes increasingly more…”
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RC-interconnect macromodels for timing simulation by Dartu, F., Tutuianu, B., Pileggi, L.T.

“…Most timing simulators obtain their efficiency over circuit simulation in terms of explicit integration algorithms that have difficulty handling the stiff RC…”
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Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching by Seung Hoon Choi, Kunhyuk Kang, Dartu, F., Roy, K.

“…In multiple input switching (MIS) analysis, input signal alignment is one of the key factors which determines the quality and the accuracy of the approach. In…”
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Expanding the frequency range of AWE via time shifting by Shebaita, A., Amin, C., Dartu, F., Ismail, Y.

“…The new technique of time shifted moment matching (TSMM) is introduced in this paper. The TSMM technique performs moment matching (for expansion around s = 0)…”
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Expanding the frequency range of AWE via time shifting by Shebaita, A., Amin, C., Dartu, F., Ismail, Y.

“…The new technique of time shifted moment matching (TSMM) is introduced in this paper. The TSMM technique performs moment matching (for expansion around s = 0)…”
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Modeling unbuffered latches for timing analysis by Amin, C. S., Dartu, F., Ismail, Y. I.

“…Unbuffered latches are often used in high-performance designs with custom timing flows. Adding these circuits to a standard library enables improved designs…”
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TETA: transistor-level engine for timing analysis by Dartu, Florentin, Pileggi, Lawrence T.

“…TETA is an interconnect-centric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and…”
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Timed pattern generation for noise-on-delay calculation by Seung Hoon Choi, Dartu, F., Roy, K.

“…Computing the effects of noise on delay is required for all circuits from simple ASIC designs to microprocessors. Transistor-level simulation engines make…”
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Timed pattern generation for noise-on-delay calculation by Choi, Seung Hoon, Roy, Kaushik, Dartu, Florentin

“…Computing the noise on delay effects is required for all circuits from simple ASIC designs to microprocessors. Transistor-level simulation engines make…”
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Calculating worst-case gate delays due to dominant capacitance coupling by Dartu, F., Pileggi, L.T.

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Algorithms for MIS Vector Generation and Pruning by Stevens, K.S., Dartu, F.

“…The main reason to omit this effect is the run time penalty and potential over-conservatism. Run times are directly proportional to the vector sizes. Efficient…”
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Piecewise linear macromodels for elementary logic and fuzzy circuits by Tesu, I.C., Dartu, F.

“…Based on a vector sorting method using piecewise linear (PWL) techniques, a piecewise linear representation for elementary logic and fuzzy circuits is derived…”
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