Search Results - "Danjo, Takumi"
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1
On-Die Monitoring of Substrate Coupling for Mixed-Signal Circuit Isolation
Published in Japanese Journal of Applied Physics (01-04-2007)Get full text
Journal Article -
2
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC
Published in IEEE journal of solid-state circuits (01-04-2015)“…Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve…”
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Journal Article -
3
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS
Published in IEEE journal of solid-state circuits (01-03-2014)“…A 6-bit, 1-GS/s subranging analog-to-digital converter (ADC) implemented in 65-nm CMOS is developed. The same capacitor DACs (CDACs) are used to sample the…”
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Journal Article -
4
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process
Published in IEEE journal of solid-state circuits (01-12-2013)“…A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind…”
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Journal Article Conference Proceeding -
5
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01-01-2016)“…With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline…”
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Conference Proceeding -
6
MLPerf™ HPC: A Holistic Benchmark Suite for Scientific Machine Learning on HPC Systems
Published in 2021 IEEE/ACM Workshop on Machine Learning in High Performance Computing Environments (MLHPC) (01-11-2021)“…Scientific communities are increasingly adopting machine learning and deep learning models in their applications to accelerate scientific insights. High…”
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Conference Proceeding -
7
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01-02-2013)“…In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current…”
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Conference Proceeding -
8
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique
Published in 2014 Symposium on VLSI Circuits Digest of Technical Papers (01-06-2014)“…Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed…”
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Conference Proceeding -
9
MLPerf HPC: A Holistic Benchmark Suite for Scientific Machine Learning on HPC Systems
Published 21-10-2021“…Scientific communities are increasingly adopting machine learning and deep learning models in their applications to accelerate scientific insights. High…”
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Journal Article -
10
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS
Published in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (01-06-2016)“…28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the…”
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Conference Proceeding -
11
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS
Published in Proceedings of Technical Program of 2012 VLSI Design, Automation and Test (01-04-2012)“…A 6b 1GS/s subranging ADC with interpolating technique, which has neither a reference resistor ladder nor redundant comparators is presented. Each comparator…”
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Conference Proceeding