Search Results - "Danjo, Takumi"

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    Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC by Yoshioka, Kentaro, Saito, Ryo, Danjo, Takumi, Tsukamoto, Sanroku, Ishikuro, Hiroki

    Published in IEEE journal of solid-state circuits (01-04-2015)
    “…Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve…”
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    Journal Article
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    A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS by Danjo, Takumi, Yoshioka, Masato, Isogai, Masayuki, Hoshino, Masanori, Tsukamoto, Sanroku

    Published in IEEE journal of solid-state circuits (01-03-2014)
    “…A 6-bit, 1-GS/s subranging analog-to-digital converter (ADC) implemented in 65-nm CMOS is developed. The same capacitor DACs (CDACs) are used to sample the…”
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    Journal Article
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    A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process by Doi, Yoshiyasu, Shibasaki, Takayuki, Danjo, Takumi, Chaivipas, Win, Hashida, Takusi, Miyaoka, Hiroki, Hoshino, Masanori, Koyanagi, Yoichi, Yamamoto, Takuji, Tsukamoto, Sanroku, Tamura, Hirotaka

    Published in IEEE journal of solid-state circuits (01-12-2013)
    “…A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind…”
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    Journal Article Conference Proceeding
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    32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS by Doi, Y., Shibasaki, T., Danjo, T., Chaivipas, W., Hashida, T., Miyaoka, H., Hoshino, M., Koyanagi, Y., Yamamoto, T., Tsukamoto, S., Tamura, H.

    “…In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current…”
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    Conference Proceeding
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    7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique by Yoshioka, Kentaro, Saito, Ryo, Danjo, Takumi, Tsukamoto, Sanroku, Ishikuro, Hiroki

    “…Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed…”
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    Conference Proceeding
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    A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS by Danjo, T., Yoshioka, M., Isogai, M., Hoshino, M., Tsukamoto, S.

    “…A 6b 1GS/s subranging ADC with interpolating technique, which has neither a reference resistor ladder nor redundant comparators is presented. Each comparator…”
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    Conference Proceeding