Search Results - "Dandapat, Anup"
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Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Published in IEEE transactions on very large scale integration (VLSI) systems (01-10-2015)“…In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported…”
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Match‐line control unit for power and delay reduction in hybrid CAM
Published in IET circuits, devices & systems (01-05-2021)“…Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look‐up in network routers and data processing…”
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3
Vedic algorithm for cubic computation and VLSI implementation
Published in Engineering science and technology, an international journal (01-10-2017)“…Algorithm of cubic computation and its VLSI implementation is described in this paper through ‘Vedic mathematics’ formulae. An N-bit cubic implementation…”
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Vedic division methodology for high-speed very large scale integration applications
Published in Journal of engineering (Stevenage, England) (01-02-2014)“…Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ‘Dhvajanka (on top…”
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Methodologies for CAM and ADC design
Published in CSI TRANSACTIONS ON ICT (01-06-2019)“…Amount of information exchange in modern technology era is increasing rapidly for accommodating both correlated and non-correlated contents. This can be best…”
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Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage
Published in IEEE transactions on circuits and systems. II, Express briefs (01-06-2017)“…Ternary content-addressable memory (TCAM) is a hardware search engine that is used to speed up searching through prestored contents rather than addresses. A…”
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EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control
Published in IEEE transactions on very large scale integration (VLSI) systems (01-06-2016)“…A ternary content addressable memory (TCAM) speeds up the search process in the memory by searching through prestored contents rather than addresses. The…”
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A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications
Published in IEEE transactions on circuits and systems. I, Regular papers (01-11-2016)“…Hardware search engine (HSE) plays a major role to speed up the search operation in wireless applications. Ternary content addressable memory (TCAM) is such an…”
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Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications
Published in IEEE transactions on circuits and systems. I, Regular papers (01-07-2020)“…Hardware search engines (HSEs) have been drawing significant attention in replacing software search algorithms in order to speed up location access and data…”
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Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine
Published in Integration (Amsterdam) (01-09-2024)“…Single clock cycle access feature of content-addressable memory (CAM) suits well for high-speed parallel content search operation in data-intensive hardware…”
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Self-Controlled High-Performance Precharge-Free Content-Addressable Memory
Published in IEEE transactions on very large scale integration (VLSI) systems (01-08-2017)“…Content-addressable memory (CAM) is a hardware searchengine used for parallel lookup that assures high-speed match but at the cost of higher power consumption…”
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SMS-CAM: Shared matchline scheme for content addressable memory
Published in Integration (Amsterdam) (01-01-2023)“…Content addressable memory (CAM) is a hardware search engine (HSE) used for accelerating lookup functions in tagged cache, translation lookaside buffers (TLBs)…”
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A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme
Published in IEEE transactions on circuits and systems. I, Regular papers (01-05-2018)“…Hardware search using content addressable memory (CAM) produces the fastest upshot but takes larger design area and consumes relatively high power. Dynamic CAM…”
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Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory
Published in IEEE transactions on consumer electronics (01-08-2018)“…Hardware search engines are widely used in network routers for high-speed look up and parallel data processing. Content addressable memory (CAM) is such an…”
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Low discharge precharge free matchline structure for energy-efficient search using CAM
Published in Integration (Amsterdam) (01-11-2019)“…Design of associative memories such as content addressable memories (CAMs) is a challenging task as the demand of high search speed and low power are given the…”
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Low-power content addressable memory design using two-layer P-N match-line control and sensing
Published in Integration (Amsterdam) (01-11-2020)“…Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation…”
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A 10-bit 2.5 GS/s low power hybrid subranging flash-SAR ADC for high data rate communication
Published in CSI TRANSACTIONS ON ICT (2018)“…The growing need for power aware and energy efficient analog-to-digital converters (ADCs) has led to the development of optimized ADC designs. Though several…”
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The analogy of matchline sensing techniques for content addressable memory (CAM)
Published in Chronic diseases and translational medicine (01-05-2020)“…Performance of a memory depends on the storage stability, yield and sensing speed. Differential input and the latching time of sense amplifiers are considered…”
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A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry
Published in Analog integrated circuits and signal processing (15-08-2019)“…Successive-approximation-register (SAR) ADC has gained popularity owing to its low power consumption in the growing field of ADC development. This work…”
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A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access
Published in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) (01-01-2017)“…Sense amplifiers provide amplification to the very small voltage change in the memory datapath in near-zero access time. The sub-micron technology demands high…”
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