Search Results - "Daga, Ajay J."

Automated timing model generation by Daga, Ajay J., Mize, Loa, Sripada, Subramanyam, Wolff, Chris, Wu, Qiuyang

“…The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical…”
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The minimization and decomposition of interface state machines by Daga, Ajay J., Birmingham, William P.

“…There is a well-recognized need for accurate timing-verification tools that account for the functional behavior of component interfaces, and thereby do not…”
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Automated timing model generation by Daga, A.J., Mize, L., Sripada, S., Wolff, C., Qiuyang Wu

“…The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical…”
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Interface finite-state machines: definition, minimization, and decomposition by Daga, A.J., Birmingham, W.P.

“…There is a well-recognized need for accurate timing verification tools that account for the functional behavior of component interfaces, and thereby do not…”
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