Search Results - "Daewon Ha"

Analog reservoir computing via ferroelectric mixed phase boundary transistors by Kim, Jangsaeng, Park, Eun Chan, Shin, Wonjun, Koo, Ryun-Han, Han, Chang-Hyeon, Kang, He Young, Yang, Tae Gyu, Goh, Youngin, Lee, Kilho, Ha, Daewon, Cheema, Suraj S., Jeong, Jae Kyeong, Kwon, Daewoong

“…Analog reservoir computing (ARC) systems have attracted attention owing to their efficiency in processing temporal information. However, the distinct…”
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Device modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression by Kim, Donguk, Kim, Je-Hyuk, Choi, Woo Sik, Yang, Tae Jun, Jang, Jun Tae, Belmonte, Attilio, Rassoul, Nouredine, Subhechha, Subhali, Delhougne, Romain, Kar, Gouri Sankar, Lee, Wonsok, Cho, Min Hee, Ha, Daewon, Kim, Dae Hwan

“…Amorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the…”
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Observation of bulk HfO2 defects by spectroscopic ellipsometry by Takeuchi, Hideki, Ha, Daewon, King, Tsu-Jae

“…Spectroscopic ellipsometry was used to investigate the oxidation of pure Hf films on silicon for the formation of HfO2 (hafnium oxide) gate-dielectric films in…”
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Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications by Daewon Ha, Yang, C., Lee, J., Lee, S., Lee, S. H., Seo, K.-I, Oh, H. S., Hwang, E. C., Do, S. W., Park, S. C., Sun, M.-C, Kim, D. H., Lee, J. H., Kang, M. I., Ha, S.-S, Choi, D. Y., Jun, H., Shin, H. J., Kim, Y. J., Moon, C. W., Cho, Y. W., Park, S. H., Son, Y., Park, J. Y., Lee, B. C., Kim, C., Oh, Y. M., Park, J. S., Kim, S. S., Kim, M. C., Hwang, K. H., Nam, S. W., Maeda, S., Kim, D.-W, Lee, J.-H, Liang, M. S., Jung, E. S.

“…7nm CMOS FinFET technology featuring EUV lithography, 4 th gen. dual Fin and 2 nd gen. multi-eWF gate stack is presented, providing 20% faster speed or…”
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Extremely scaled silicon nano-CMOS devices by Chang, L., Yang-kyu Choi, Ha, D., Ranade, P., Shiying Xiong, Bokor, J., Chenming Hu, King, T.J.

“…Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator…”
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Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs by Daewon Ha, Takeuchi, H., Yang-Kyu Choi, Tsu-Jae King

“…Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully…”
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Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs by Choi, Yang-Kyu, Ha, Daewon, King, Tsu-Jae, Bokor, Jeffrey

“…Gate-induced drain leakage (GIDL) current is investigated in single-gate (SG) ultra-thin body FET, symmetrical double-gate (DG) FinFET, and asymmetrical DG…”
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Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs by Jeong-Soo Lee, Yang-Kyu Choi, Daewon Ha, Balasubramanian, S., Tsu-Jae King, Bokor, J.

“…The hydrogen annealing process has been used to improve surface roughness of the Si-fin in CMOS FinFETs for the first time. Hydrogen annealing was performed…”
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Progress, Challenges, and Opportunities in Oxide Semiconductor Devices: A Key Building Block for Applications Ranging from Display Backplanes to 3D Integrated Semiconductor Chips by Kim, Taikyu, Choi, Cheol Hee, Hur, Jae Seok, Ha, Daewon, Kuh, Bong Jin, Kim, Yongsung, Cho, Min Hee, Kim, Sangwook, Jeong, Jae Kyeong

“…As Si has faced physical limits on further scaling down, novel semiconducting materials such as 2D transition metal dichalcogenides and oxide semiconductors…”
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Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain by Choi, Yang-Kyu, Ha, Daewon, King, Tsu-Jae, Hu, Chenming

“…Nanoscale ultrathin body (UTB) p-channel MOSFETs with body thickness down to 4 nm and raised source and drain (S/D) using selectively deposited Ge are…”
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Design Guidelines of Multibridge Channel-Ferroelectric FET for 3-nm Node and Beyond by Lee, Kynghwan, Hong, Jungpyo, Kuh, Bong Jin, Ha, Daewon, Hyun, Sangjin, Ahn, Sujin, Song, Jaihyuk

“…Multibridge channel-ferroelectric field-effect transistor (MBC-FeFET) with metal-ferroelectric-metal-insulator-silicon (MFMIS) gate-stack is an advanced noble…”
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A Comprehensive Study of Transient Characteristics in FeFET Using In-Situ V t Measurement Method by Myeong, Ilho, Kim, Hyoseok, Kim, Wanki, Ha, Daewon, Ahn, Sujin, Song, Jaihyuk

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A Comprehensive Study of Transient Characteristics in FeFET Using In-Situ Vt Measurement Method by Myeong, Ilho, Kim, Hyoseok, Kim, Wanki, Ha, Daewon, Ahn, Sujin, Song, Jaihyuk

“…In ferroelectric FETs (FeFETs), the transient characteristics is a key issue to be addressed. Therefore, it is important to have an understanding based on…”
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Prospective Innovation of DRAM, Flash, and Logic Technologies for Digital Transformation (DX) Era by Ha, Daewon, Kim, Hyoung-Sub

“…DX (digital transformation) is expected to lead a steeper acceleration in the growth trajectory and open a greater opportunity in the semiconductor industry…”
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Revival of Ferroelectric Memories Based on Emerging Fluorite-Structured Ferroelectrics by Park, Ju Yong, Choe, Duk-Hyun, Lee, Dong Hyun, Yu, Geun Taek, Yang, Kun, Kim, Se Hyun, Park, Geun Hyeong, Nam, Seung-Geol, Lee, Hyun Jae, Jo, Sanghyun, Kuh, Bong Jin, Ha, Daewon, Kim, Yongsung, Heo, Jinseong, Park, Min Hyuk

“…Over the last few decades, the research on ferroelectric memories has been limited due to their dimensional scalability and incompatibility with complementary…”
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Understanding the Memory Window of Ferroelectric FET and Demonstration of 4.8-V Memory Window With 20-nm HfO 2 by Qin, Yixin, Zhao, Zijian, Lim, Suhwan, Kim, Kijoon, Kim, Kwangsoo, Kim, Wanki, Ha, Daewon, Narayanan, Vijaykrishnan, Ni, Kai

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Understanding the Memory Window of Ferroelectric FET and Demonstration of 4.8-V Memory Window With 20-nm HfO2 by Qin, Yixin, Zhao, Zijian, Lim, Suhwan, Kim, Kijoon, Kim, Kwangsoo, Kim, Wanki, Ha, Daewon, Narayanan, Vijaykrishnan, Ni, Kai

“…In this work, with the goal of developing a large memory window (MW) ferroelectric field-effect transistor (FeFET) for high-density stand-alone storage…”
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Strategies for a Wide Memory Window of Ferroelectric FET for Multilevel Ferroelectric VNAND Operation by Myeong, Ilho, Kim, Hyoseok, Kim, Seunghyun, Lim, Suhwan, Kim, Kwangsu, Kim, Wanki, Ha, Daewon, Ahn, Sujin, Song, Jaihyuk

“…Basic gate stack structure of the Ferroelectric FET is Metal-ferroelectric-insulator-silicon (MFIS), where the memory window (M.W) is <inline-formula>…”
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Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices by Ha, Daewon, Cho, Changhyun, Shin, Dongwon, Koh, Gwan-Hyeob, Chung, Tae-Young, Kim, Kinam

“…As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced…”
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A Large Window Nonvolatile Transistor Memory for High-Density and Low-Power Vertical NAND Storage Enabled by Ferroelectric Charge Pumping by Zhao, Zijian, Qin, Yixin, Duan, Jiahui, Lee, YuShan, Lim, Suhwan, Kim, Kijoon, Kim, Kwangsoo, Kim, Wanki, Ha, Daewon, Narayanan, Vijaykrishnan, Ni, Kai

“…In this work, we have developed a large memory window (MW) ferroelectric field effect transistor (FeFET) memory for vertical NAND storage. We demonstrate that:…”
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