Search Results - "Dae-Gwan Kang"

Prediction of data retention time distribution of DRAM by physics-based statistical Simulation by Seonghoon Jin, Jeong-Hyong Yi, Jae Hoon Choi, Dae Gwan Kang, Park, Y.J., Hong Shick Min

“…We have developed a comprehensive TCAD framework that can predict the data retention time distribution of a dynamic random access memory (DRAM) chip using the…”
Get full text

A New Direct Evaluation Method to Obtain the Data Retention Time Distribution of DRAM by JIN, Seonghoon, MYOUNG JIN LEE, YI, Jeong-Hyong, JAE HOON CHOI, DAE GWAN KANG, CHUNG, In-Young, YOUNG JUNE PARK, HONG SHICK MIN

“…The authors have developed an efficient and accurate method to obtain the data retention time distribution of DRAM from the physics-based device simulation and…”
Get full text

The Simulation of the Dynamic Characteristics of Friction Stir Welding and the Structural Deflection of Base Materials by Cha, Woon-Yong, Im, Se-Bin, Kim, Jae-Won, Kang, Dae-Gwan

“…Friction stir welding requires an optimized process because the quality of the weld can vary depending on the dynamic characteristics of the welding tool. In…”
Get full text

Modeling alpha-particle-induced accelerated soft error rate in semiconductor memory by Gong, Myeong Kook, Kim, Do Woo, Lee, Chang Yeol, Choi, Deuk Sung, Kang, Dae-Gwan

“…This paper presents an analytic integral model for the accelerated soft error rate (ASER). The model took into account the physical and structural parameters…”
Get full text

Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain N-channel metal-oxide-semiconductor field effect transistors by JUNG-SUK GOO, HYUNGSOON SHIN, HYUNSANG HWANG, DAE-GWAN KANG, DONG-HYUK JU

“…This paper experimentally demonstrates that hot carrier degradation curves of lightly doped drain n-channel metal-oxide-semiconductor field effect transistors…”
Get full text

Impact of Nitrogen Implantation in Lightly Doped Drain (NIL) on Deep Sub-Micron CMOS Devices by Hong, S-K, Lee, S-G, Lee, K-H, Ahn, J-G, Son, J-H, Kang, D-G

“…In this study, we investigate the device characteristics of lightly doped drain (LDD) metal-oxide-semiconductor field effect transistors (MOSFETs) with…”
Get full text

Trap evaluations of metal/oxide/silicon field-effect transistors with high- k gate dielectric using charge pumping method by Lee, Ga-Won, Lee, Jae-Hee, Lee, Hae-Wang, Park, Myoung-Kyu, Kang, Dae-Gwan, Youn, Hee-Koo

“…The interface trap properties of metal/oxide/silicon field-effect transistors with high-k gate dielectrics are evaluated by the charge pumping method and…”
Get full text

Characteristics of n+–p junction leakage induced by tantalum pentoxide gate insulator and gate reoxidation by Kang, Chang-Yong, Kim, Young-Gwan, Kang, Dae-Gwan

“…This letter will present the n+–p junction characteristics in tantalum pentoxide gate dielectric (Ta2O5) and gate reoxidation ambient. The n+–p junctions in…”
Get full text

Analysis of body bias effect with PD-SOI for analog and RF applications by Lee, Hyeokjae, Nah, Hyunchul, Lee, Jong-Ho, Kang, Dae-Gwan, Park, Young June, Min, Hong Shick

“…The interaction of the body bias effect, device size, and analog characteristics such as DC gain, the matching effect, and speed ( f T and f max) of the…”
Get full text

Effects of nitrogen implantation in silicon for shallow p+-n junction formation by Kang, Chang-Yong, Cho, Won-Joo, Kang, Dae-Gwan, Lee, Young-Jong, Hwang, Jeong-Mo

“…This letter will present the effects of nitrogen implantation on shallow p+-n junction formation in silicon. The p+-n junctions fabricated at different…”
Get full text

A simple voltage scaling formula for low-power CMOS circuits by Kang, Dae-Gwan, Park, Young June, Min, Hong Shick

“…A simple formula is proposed for the analysis of the gate delay of CMOS gate under low V/sub DD/. The effects of device parameters on gate delay and energy are…”
Get full text

Current-crowding effect in diagonal MOSFET's by Hwang, H., Shin, H., Kang, D.-G., Ju, D.-H.

“…Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device…”
Get full text

Ultra thin-oxide damage from gate charging during PETEOS deposition processing by Young-Gwan Kim, Hazoong Kim, Kang-Sik Youn, Dae-Gwan Kang, Jeong-Mo Hwang

“…This paper presents a study of plasma-enhanced tetraethylorthosilicate oxide process (PETEOS) induced charging damage to thin gate oxide reliability of p-and…”
Get full text

Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits by Myoung-Jun Jang, Hi-Deok Lee, Myoung-Kyu Park, Hae-Wang Lee, Kyung-Jin Yoo, Sang-Bok Lee, Sung-Woong Chung, Dae-Gwan Kang, Jeong-Mo Hwang

“…In this paper the dependence of interconnect line-induced delay time on the repeater size is characterized. In case of capacitance dominant interconnect line,…”
Get full text

Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging by Hi-Deok Lee, Myoung-Jun Jang, Dae-Gwan Kang, Young-Jong Lee, Jeong-Mo Hwang, Dae-Mann Kim

“…Time delay, /spl tau//sub D/ due to MLM is systematically characterized in circuit operating conditions. Novel utilization of simple test patterns is shown to…”
Get full text

An anomalous device degradation of SOI devices with STI by Hyeokjae Lee, Jong Ho Lee, Dae-Gwan Kang, Young June Park, Hong Shick Min

“…The degradation of the electrical characteristics of SOI MOSFETs with STI structure is found to be dependent on the device size. The degradation is due to…”
Get full text

Performance improvements in high-density DRAM application using 0.15 /spl mu/m body-contacted SOI technology by Jong-Wook Lee, Hyung-Ki Kim, Jong-Soo Kim, Won-Chang Lee, Jeong-Hee Oh, Dae-Gwan Kang, Yo-Hwan Koh

“…A 0.15 /spl mu/m silicon-on-insulator (SOI) CMOS technology, using a body-contacted (BC) SOI structure, is developed. This process technology is fully…”
Get full text

Modeling of retention time distribution of DRAM cell using a Monte-Carlo method by JIN, Seonghoon, YI, Jeong-Hyong, JAE HOON CHOI, DAE GWAN KANG, YOUNG JUNE PARK, HONG SHICK MIN

“…A comprehensive Monte-Carlo method for the simulation of the data retention time distribution of DRAM cell has been developed using the current Green's…”
Get full text

Accurate evaluation of gate delay for low-power and high-density 0.18 /spl mu/m CMOSFET technology by Myoung-Kyu Park, Hi-Deok Lee, Myhoung-Jun Jang, Jung-Hun Choi, Dae-Gwan Kang, Jeong-Mo Hwang

“…The gate delay of ring oscillators in high V/sub T/ CMOSFET technology is characterized with respect to various channel widths (0.72 /spl mu/m-10 /spl mu/m)…”
Get full text

Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parameters by Hi-Deok Lee, Myoung-Jun Jang, Dae-Gwan Kang, Jeong-Mo Hwang, Yong-Joo Kim, Oh-Kyong Kwon, Dae-Mann Kim

“…Crosstalk-induced noise of 0.18 /spl mu/m CMOS Technology is characterized using time domain reflectometry and scattering parameters. The interconnect lines…”
Get full text