Search Results - "Dadoria, Ajay Kumar"

Ultra Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL Logic by Agrawal, Akash, Gupta, Tarun Kumar, Dadoria, Ajay Kumar

“…With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the…”
Get full text

Ultra Low Power High Speed Domino Logic Circuit by Using FinFET Technology by Dadoria, Ajay Kumar, Khare, Kavita, Gupta, Tarun Kumar, Singh, R. P.

“…Scaling of the MOSFET face greater challenge by extreme power density due to leakage current in ultra deep sub-micron (UDSM) technology. To overcome from this…”
Get full text

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology by Dadoria, Ajay Kumar, Khare, Kavita

“…Miniaturization of semiconductor industries paved the way for rapid development in the field of digital electronics. In DSM range, power dissipation has become…”
Get full text

Performance evaluation of domino logic circuits for wide fan-in gates with FinFET by Dadoria, Ajay Kumar, Khare, Kavita, Panwar, Uday, Jain, Anita

“…Power dissipation, propagation delay and noise are major issues in digital circuit design. In this paper, a new leakage-tolerant domino circuit is presented…”
Get full text

Ultra-low power FinFET-based domino circuits by Dadoria, Ajay Kumar, Khare, Kavita, Gupta, Tarun K., Singh, R. P.

“…Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase…”
Get full text

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits by Dadoria, Ajay Kumar, Khare, Kavita, Gupta, T.K., Panwar, Uday

“…Power dissipation is a main attention for designing complementary metal oxide semiconductor Very Large Scale Integration (VLSI) circuits in deep sub‐micron…”
Get full text

Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits by Dadoria, Ajay Kumar, Khare, Kavita, Gupta, Tarun K., Khare, Nilay

“…This work impacts on the huge potential of FinFET technology, which can replace bulk MOS below 32 nm. Here, two new techniques are introduced to mitigate…”
Get full text

A Novel Adiabatic Technique for Energy Efficient Logic Circuits Design by Chugh, Chetan, Kaur, Pawandeep

“…As we are moving ahead in technology, the sizes of various gadgets and devices is reducing which means we need to size down the CMOS logic cells. Adiabatic…”
Get full text

A novel efficient adiabatic logic design for ultra low power by Agrawal, Akash, Gupta, Tarun Kumar, Dadoria, Ajay Kumar, Kumar, Deepak

“…With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra…”
Get full text

Low power high speed 1-bit full adder circuit design in DSM technology by Yadav, Ashish, Shrivastava, Bhawna P., Dadoria, Ajay Kumar

“…In today's high-speed communication world the usage of electronics portable devices is increasing day by day, as the devices are portable and compact it has to…”
Get full text

Comparative analysis of various Domino logic circuits for better performance by Thakur, Ravikant, Dadoria, Ajay Kumar, Gupta, Tarun Kumar

“…In this paper, basically the delay and the noise margin parameter associated in the circuit has been analyzed. The paper gives a better approach for the…”
Get full text

Sleepy lector: A novel approach for leakage reduction in DSM technology by Dadoria, Ajay Kumar, Khare, Kavita, Singh, R. P.

“…Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (DSM) technology for CMOS circuit design. In this paper we have…”
Get full text

A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits by Dadoria, Ajay Kumar, Khare, Kavita, Singh, R. P.

“…Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the…”
Get full text

Carbon NanoTube based logic gates structure for low power consumption at nano-scaled era by Kumar, Deepak, Dadoria, Ajay Kumar, Gupta, T. K.

“…As day by day continuing research in the field of nanotechnology, the CMOS manufacturing process scaled down in nano-dimensions at the cost of severe process…”
Get full text