8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 45; no. 1; pp. 111 - 119
Main Authors:	KANG, Uksong, CHUNG, Hoe-Ju, LEE, Jae-Wook, JOO, Han-Sung, KIM, Woo-Seop, DONG HYEON JANG, NAM SEOG KIM, CHOI, Jung-Hwan, CHUNG, Tae-Gyeong, YOO, Jei-Hwan, JOO SUN CHOI, KIM, Changhyun, HEO, Seongmoo, JUN, Young-Hyun, PARK, Duk-Ha, LEE, Hoon, JIN HO KIM, AHN, Soon-Hong, CHA, Soo-Ho, AHN, Jaesung, KWON, Dukmin
Format:	Journal Article Conference Proceeding
Language:	English
Published:	New York, NY IEEE 01-01-2010 Institute of Electrical and Electronics Engineers
Subjects:	3-D architecture Applied sciences Assembly assembly yield CMOS logic circuits CMOS technology connectivity check and repair DDR3 DRAM double data rate Electronics Exact sciences and technology gapless read Integrated circuit interconnections Integrated circuits Integrated circuits by function (including memories and processors) master Master-slave module Noise reduction power edge pads power noise reduction Random access memory rank refresh seamless Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices slave stack Statistical analysis Sun three dimensional Through-silicon vias Through-silicon-via (TSV) via first via last via middle seamless stack three dimensional connectivity check and repair module refresh master slave Through-silicon-via (TSV) via first Three dimensional structure assembly yield rank double data rate Low-power electronics power edge pads power noise reduction via last via middle gapless read 3-D architecture Dynamic random access memory Via hole DDR3 DRAM
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Summary:	An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2009.2034408