Search Results - "DE KEERSGIETER, A"

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession by Chiarella, T., Witters, L., Mercha, A., Kerner, C., Rakowski, M., Ortolland, C., Ragnarsson, L.-Å., Parvais, B., De Keersgieter, A., Kubicek, S., Redolfi, A., Vrancken, C., Brus, S., Lauwers, A., Absil, P., Biesemans, S., Hoffmann, T.

“…The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its improved electrostatics and short-channel effect control…”
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Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition by Witters, L., Arimura, H., Sebaai, F., Hikavyy, A., Milenin, A. P., Loo, R., De Keersgieter, A., Eneman, G., Schram, T., Wostyn, K., Devriendt, K., Schulze, A., Lieten, R., Bilodeau, S., Cooper, E., Storck, P., Chiu, E., Vrancken, C., Favia, P., Vancoille, E., Mitard, J., Langer, R., Opdebeeck, A., Holsteyns, F., Waldron, N., Barla, K., De Heyn, V., Mocuta, D., Collaert, N.

“…Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain…”
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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails by Veloso, A., Jourdain, A., Radisic, D., Chen, R., Arutchelvan, G., O'Sullivan, B., Arimura, H., Stucchi, M., De Keersgieter, A., Hosseini, M., Hopf, T., D'have, K., Wang, S., Dupuy, E., Mannaert, G., Vandersmissen, K., Iacovo, S., Marien, P., Choudhury, S., Schleicher, F., Sebaai, F., Oniki, Y., Zhou, X., Gupta, A., Schram, T., Briggs, B., Lorant, C., Rosseel, E., Hikavyy, A., Loo, R., Geypen, J., Batuk, D., Martinez, G. T., Soulie, J. P., Devriendt, K., Chan, B. T., Demuynck, S., Hiblot, G., Van der Plas, G., Ryckaert, J., Beyer, G., Litta, E. Dentoni, Beyne, E., Horiguchi, N.

“…We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight…”
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Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates by Mertens, H., Ritzenthaler, R., Hikavyy, A., Kim, M. S., Tao, Z., Wostyn, K., Chew, S. A., De Keersgieter, A., Mannaert, G., Rosseel, E., Schram, T., Devriendt, K., Tsvetanova, D., Dekkers, H., Demuynck, S., Chasin, A., Van Besien, E., Dangol, A., Godny, S., Douhard, B., Bosman, N., Richard, O., Geypen, J., Bender, H., Barla, K., Mocuta, D., Horiguchi, N., Thean, A. V-Y

“…We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which…”
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Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling by Veloso, A., Eneman, G., De Keersgieter, A., Favia, P., Hikavyy, A., Chen, R., Jourdain, A., Horiguchi, N.

“…We report on vertically stacked nanosheet (NS) FETs, focusing on the combined inner spacers and source/drain (S/D) epitaxial growth modules sequence, a key…”
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Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass by Kikuchi, Y., Chiarella, T., De Roest, D., Blanquart, T., De Keersgieter, A., Kenis, K., Peter, A., Ong, P., Van Besien, E., Tao, Z., Kim, M. S., Kubicek, S., Chew, S. A., Schram, T., Demuynck, S., Mocuta, A., Mocuta, D., Horiguchi, N.

“…For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this…”
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Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning by Mertens, H., Hosseini, M., Chiarella, T., Zhou, D., Wang, S., Mannaert, G., Dupuy, E., Radisic, D., Tao, Z., Oniki, Y., Hikavyy, A., Rosseel, R., Mingardi, A., Choudhury, S., Gowda, P. Puttarame, Sebaai, F., Peter, A., Vandersmissen, K., Soulie, J.P., Keersgieter, A. De, Lima, L. Petersen Barbosa, Cavalcante, C., Batuk, D., Martinez, G.T., Geypen, J., Seidel, F., Paulussen, K., Favia, P., Boemmels, J., Loo, R., Wong, P., Marquez, A. Sepulveda, Chan, B.T., Mitard, J., Subramanian, S., Demuynck, S., Litta, E. Dentoni, Horiguchi, N., Samavedam, S., Biesemans, S.

“…We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD…”
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Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS by Veloso, A., Hellings, G., Cho, M. J., Simoen, E., Devriendt, K., Paraschiv, V., Vecchio, E., Tao, Z., Versluijs, J. J., Souriau, L., Dekkers, H., Brus, S., Geypen, J., Lagrain, P., Bender, H., Eneman, G., Matagne, P., De Keersgieter, A., Fang, W., Collaert, N., Thean, A.

“…We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW)…”
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Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study by Eneman, G., Verheyen, P., De Keersgieter, A., Jurczak, M., De Meyer, K.

“…This paper presents a study on the effectiveness of strained contact-etch-stop-layer (CESL) technologies in aggressively scaled dense structures. The focus is…”
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Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity by Augendre, E., Rooyackers, R., Caymax, M., Vandamme, E.P., De Keersgieter, A., Perello, C., Van Dievel, M., Pochet, S., Badenes, G.

“…The continuous downscaling of CMOS devices aims at cost reduction and performance improvement. Process development constantly faces new constraints and…”
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Performance improvement of tall triple gate devices with strained SiN layers by Collaert, N., De Keersgieter, A., Anil, K.G., Rooyackers, R., Eneman, G., Goodwin, M., Eyckens, B., Sleeckx, E., de Marneffe, J.-F., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S.

“…In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and…”
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Consistent model for short-channel nMOSFET after hard gate oxide breakdown by Kaczer, B., Degraeve, R., De Keersgieter, A., Van de Mieroop, K., Simons, V., Groeseneken, G.

“…Dissimilar post-hard-breakdown nMOSFET characteristics are consistently explained by the location of a constant-size breakdown path. Device simulations with…”
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Quantum-barriers and ground-plane isolation: A path for scaling bulk-FinFET technologies to the 7 nm-node and beyond by Eneman, G., Hellings, G., De Keersgieter, A., Collaert, N., Thean, A.

“…The electrostatic integrity of 7 nm-node bulk FinFETs (FF) is studied by TCAD. Lowly-doped bulk-FF have worse electrostatics than SOI- and GeOI-FF. However, by…”
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Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory by Van den bosch, G., Kar, G. S., Blomme, P., Arreghini, A., Cacciato, A., Breuil, L., De Keersgieter, A., Paraschiv, V., Vrancken, C., Douhard, B., Richard, O., Van Aerde, S., Debusschere, I., Van Houdt, J.

“…A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We…”
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A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions by Sasaki, Y., Ritzenthaler, R., De Keersgieter, A., Chiarella, T., Kubicek, S., Rosseel, E., Waite, A., del Agua Borniquel, J., Colombeau, B., Chew, S. A., Kim, M. S., Schram, T., Demuynck, S., Vandervorst, W., Horiguchi, N., Mocuta, D., Mocuta, A., Thean, A. V.-Y

“…We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved I ON , +15% with Room Temperature (RT)…”
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Relation between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications by Degraeve, R., Kaczer, B., De Keersgieter, A., Groeseneken, G.

“…A method to determine the breakdown position in short channel nMOSFETs is introduced. We find that soft breakdown occurs exclusively in the transistor channel…”
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Nanosheet-based Device Architectures with Front/Backside Connectivity: Opportunities for S/D Engineering to Enable Advanced CMOS Logic Scaling by Veloso, A., Eneman, G., Matagne, P., Keersgieter, A. De, Hikavyy, A., Favia, P., Horiguchi, N.

“…We report on nanosheet-based FETs as key enablers for the continuation of the CMOS logic scaling roadmap beyond finFETs. Their source/drain (S/D) definition is…”
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Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling by Veloso, A., Eneman, G., de Keersgieter, A., Jang, D., Mertens, H., Matagne, P., Litta, E. Dentoni, Ryckaert, J., Horiguchi, N.

“…We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue delivering profitable node to node scaling gains. Key fabrication…”
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New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs by Crupi, F., Kaczer, B., Groeseneken, G., De Keersgieter, A.

“…In this letter, we report new findings in the relation between channel hot-carrier (CHC) degradation and gate-oxide breakdown (BD) in short-channel nMOSFETS…”
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A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C by Collaert, N, Aoulaiche, M, De Wachter, B, Rakowski, M, Redolfi, A, Brus, S, De Keersgieter, A, Horiguchi, N, Altimime, L, Jurczak, M

“…Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in…”
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