Search Results - "Cosnier, V."

Measurement of Dipoles/Roll-Off /Work Functions by Coupling CV and IPE and Study of Their Dependence on Fabrication Process by Charbonnier, Matthieu, Leroux, Charles, Cosnier, V, Besson, P, Martinez, E, Benedetto, N, Licitra, Christophe, Rochat, Névine, Gaumer, C, Kaja, K, Ghibaudo, Gérard, Martin, François, Reimbold, Gilles

“…We study the effective metal gate work function (WF Meff ) of different metal/high-κ gate stacks. Both capacitance versus voltage measurement and internal…”
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Performance and reliability of advanced High-K/Metal gate stacks (Invited Paper) by Garros, X., Casse, M., Reimbold, G., Rafik, M., Martin, F., Andrieu, F., Cosnier, V., Boulanger, F.

“…This paper provides a systematic study of mobility performance and Bias Temperature Instabilities (BTI) reliability in advanced dielectrics stacks. By studying…”
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Surface preparation and interfacial stability of high-k dielectrics deposited by atomic layer chemical vapor deposition by Tsai, W., Carter, R.J., Nohira, H., Caymax, M., Conard, T., Cosnier, V., DeGendt, S., Heyns, M., Petry, J., Richard, O., Vandervorst, W., Young, E., Zhao, C., Maes, J., Tuominen, M., Schulte, W.H., Garfunkel, E., Gustafsson, T.

“…The effects of various interface preparations on atomic layer chemical vapor deposition (ALCVD) deposited Al 2O 3 and ZrO 2 dielectrics properties were…”
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Understanding of the thermal stability of the hafnium oxide/TiN stack via 2 “high k” and 2 metal deposition techniques by Cosnier, V., Besson, P., Loup, V., Vandroux, L., Minoret, S., Cassé, M., Garros, X., Pedini, J-M., Lhostis, S., Dabertrand, K., Morin, C., Wiemer, C., Perego, M., Fanciulli, M.

“…In this work we evaluate the impact of the gate stack layers deposition technologies and their combination on the thermal stability of the stack with respect…”
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Tuning the dipole at the High-κ/SiO2 interface in advanced metal gate stacks by Charbonnier, M., Leroux, C., Cosnier, V., Besson, P., Martin, F., Ghibaudo, G., Reimbold, G.

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HfO2–SiO2 interface in PVD coatings by Cosnier, V., Olivier, M., Théret, G., André, B.

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Tuning the dipole at the High-[kappa]/SiO@@d2@ interface in advanced metal gate stacks by Charbonnier, M, Leroux, C, Cosnier, V, Besson, P, Martin, F, Ghibaudo, G, Reimbold, G

“…Combining two different electrical characterisation methods on the same MOS capacitors, we demonstrate that the flat band voltage of High-[kappa] metal gate…”
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Measurement of Dipoles/Roll-Off /Work functions by coupling CV and IPE and study of their dependence on fabrication process by Charbonnier, M., Leroux, Cédric, Cosnier, V., Besson, P., Martinez, E., Benedetto, N., Licitra, C., Rochat, N., Gaumer, C., Kaja, K., Ghibaudo, G., Martin, F., Reimbold, G.

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Tuning the dipole at the High-/SiO2 interface in advanced metal gate stacks by Charbonnier, M., Leroux, Cédric, Cosnier, V., Besson, P., Martin, F., Ghibaudo, G., Reimbold, G.

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Tuning the dipole at the High-κ/SiO 2 interface in advanced metal gate stacks by Charbonnier, M., Leroux, C., Cosnier, V., Besson, P., Martin, F., Ghibaudo, G., Reimbold, G.

“…Combining two different electrical characterisation methods on the same MOS capacitors, we demonstrate that the flat band voltage of High-κ metal gate stack is…”
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Guidelines to improve mobility performances and BTI reliability of advanced high-k/metal gate stacks by Garros, X., Casse, M., Reimbold, G., Martin, F., Leroux, C., Fanton, A., Renault, O., Cosnier, V., Boulanger, F.

“…A systematic study of mobility performances and BTI reliability was done in advanced dielectrics stacks. By reducing the oxide films thicknesses T HK les2.5…”
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Effect of N2 annealing on AlZrO oxide by Pétry, J., Richard, O., Vandervorst, W., Conard, T., Chen, J., Cosnier, V.

“…In the path to the introduction of high-k dielectric into integrated circuit components, a large number of challenges has to be solved. Subsequent to the film…”
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Understanding of the thermal stability of the hafnium oxide/TiN stack via 2 "high k" and 2 metal deposition techniques by Cosnier, V., Besson, P., Loup, V., Vandroux, L., Minoret, S., Casse, M., Garros, X., Pedini, Jm, Lhostis, S., Dabertrand, K., Morin, Céline, Wiemer, C., Perego, M., Fanciulli, M.

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Tuning the dipole at the High-k/SiO2 interface in advanced metal gate stacks by CHARBONNIER, M, LEROUX, C, COSNIER, V, BESSON, P, MARTIN, F, GHIBAUDO, G, REIMBOLD, G

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Thermal stability and scalability of Zr-aluminate-based high-k gate stacks by Chen, P.J., Cartier, E., Carter, R.J., Kauerauf, T., Zhao, C., Petry, J., Cosnier, V., Xu, Z., Kerber, A., Tsai, W., Young, E., Kubicek, S., Caymax, M., Vandervorst, W., De Gendt, S., Heyns, M., Copel, M., Besling, W.F.A., Bajolet, P., Maes, J.

“…It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the…”
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Reliable extraction of metal gate work function by combining two electrical characterization methods by Charbonnier, M., Mitard, J., Leroux, C., Ghibaudo, G., Cosnier, V., Besson, P., Martin, F., Reimbold, G.

“…In this paper, we extract the gate work function of metal/High-K stacks (WF M ) with an internal photoemission (IPE) based method and a C(V) characterization…”
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HfO 2 – SiO 2 interface in PVD coatings by Cosnier, V., Olivier, M., Théret, G., André, B.

“…Hafnium oxide presents a strong interest either for optical coatings or for microelectronic applications. An important parameter to control is its chemical…”
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Effect of N 2 annealing on AlZrO oxide by Pétry, J., Richard, O., Vandervorst, W., Conard, T., Chen, J., Cosnier, V.

“…In the path to the introduction of high-k dielectric into integrated circuit components, a large number of challenges has to be solved. Subsequent to the film…”
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HfO sub(2)-SiO sub(2) interface in PVD coatings by Cosnier, V, Olivier, M, Theret, G, Andre, B

“…The interface between HfO sub(2) and SiO sub(2) in electron beam evaporated coatings were analyzed using multiple infrared reflection (MIR) technique and X-ray…”
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Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications by Bidal, G., Boeuf, F., Denorme, S., Loubet, N., Laviron, C., Leverd, F., Barnola, S., Salvetat, T., Cosnier, V., Martin, F., Grosjean, M., Perreau, P., Chanemougame, D., Haendler, S., Marin, M., Rafik, M., Fleury, D., Leyris, C., Clement, L., Sellier, M., Monfray, S., Bougueon, J., Samson, M.P., Chapon, J.D., Gouraud, P., Ghibaudo, G., Skotnicki, T.

“…This work highlights the new bulk + technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low…”
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