Search Results - "Civale, Y"

Fine pitch Cu/Sn solid state diffusion bonding for making high yield bump interconnections and its application in 3D integration by Zhang, W, Limaye, P, Civale, Y, Labie, R, Soussan, P

“…Low temperature stacking of dies for 3D integration has been gaining interest due to the thermal sensitivity of some advanced node devices such as DRAM…”
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A novel concept for ultra-low capacitance via-last TSV by Civale, Y, Gonzalez, M, Tezcan, D S, Travaly, Y, Soussan, P, Beyne, E

“…In this study, we report a new concept of through silicon via for 3D applications requiring ultra-low coupling capacitance. The challenges linked to the…”
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3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias by Civale, Y, Tezcan, D S, Philipsen, H G G, Duval, F F C, Jaenen, P, Travaly, Y, Soussan, P, Swinnen, B, Beyne, E

“…In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a…”
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Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications by Duval, F F C, Okoro, C, Civale, Y, Soussan, P, Beyne, E

“…Ring-shaped silicon trenches with a depth of 50 were filled with different spin-on dielectric (SOD) polymers. Ultimately, the polymer should serve as deep…”
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Selective Solid-Phase Silicon Epitaxy of p super(+) Aluminum-Doped Contacts for Nanoscale Devices by Civale, Y, Nanver, L K, Schellevis, H

“…A solid-phase epitaxy (SPE) process based on material inversion of an amorphous silicon (alpha-Si) on aluminum layer-stack is applied to form ultrashallow…”
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On the thermal stability of physically-vapor-deposited diffusion barriers in 3D Through-Silicon Vias during IC processing by Civale, Yann, Croes, Kristof, Miyamori, Yuichi, Velenis, Dimitrios, Redolfi, Augusto, Thangaraju, Sarasvathi, Ammel, Annemie Van, Cherman, Vladimir, Plas, Geert Van der, Cockburn, Andrew, Gravey, Virginie, Kumar, Nirajan, Cao, Zhitao, Travaly, Youssef, Tőkei, Zsolt, Beyne, Eric, Swinnen, Bart

“…Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and…”
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Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes by Civale, Y., Nanver, L.K., Hadley, P., Goudena, E.J.G., Schellevis, H.

“…A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and…”
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Sub-500 °C solid-phase epitaxy of ultra-abrupt p+-silicon elevated contacts and diodes by CIVALE, Yann, NANVER, Lis K, HADLEY, Peter, GOUDENA, Egbert J. G, SCHELLEVIS, Hugo

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Impact of barrier integrity on liner reliability in 3D through silicon vias by Yunlong Li, Civale, Y., Oba, Y., Cockburn, A., Jin Hee Park, Beyne, E., De Wolf, I., Croes, K.

“…For 3D chip stacking using Cu through silicon vias (TSV's), dielectric liner reliability is crucial and is closely related to the barrier integrity. In this…”
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Selective solid-phase silicon epitaxy of p+ aluminum-doped contacts for nanoscale devices by CIVALE, Yann, NANVER, Lis K, SCHELLEVIS, Hugo

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Sub-500 deg C solid-phase epitaxy of ultra-abrupt p/sup %2B/-silicon elevated contacts and diodes by Civale, Y, Nanver, L K, Hadley, P, Goudena, E J G, Schellevis, H

“…A well-controlled low-temperature process, demonstrated from 350 deg C to 500 deg C, has been developed for epitaxially growing elevated contacts and…”
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Sub-500 deg C solid-phase epitaxy of ultra-abrupt p+-silicon elevated contacts and diodes by Civale, Y, Nanver, L K, Hadley, P, Goudena, E J G, Schellevis, H

“…A well-controlled low-temperature process, demonstrated from 350 deg C to 500 deg C, has been developed for epitaxially growing elevated contacts and…”
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Effect of TSV presence on FEOL yield and reliability by Kauerauf, T., Branka, A., Croes, K., Redolfi, A., Civale, Y., Torregiani, C., Groeseneken, G., Beyne, E.

“…In this work we evaluate the impact of TSV processing and proximity on transistor performance and reliability by monitoring key device parameters after thermal…”
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Sub-500 degree C solid-phase epitaxy of ultra-abrupt p super(+)-silicon elevated contacts and diodes by Civale, Y, Nanver, L K, Hadley, P, Goudena, EJG, Schellevis, H

“…A well-controlled low-temperature process, demonstrated from 350 degree C to 500 degree C, has been developed for epitaxially growing elevated contacts and…”
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Selective Solid-Phase Silicon Epitaxy of }^ Aluminum-Doped Contacts for Nanoscale Devices by Civale, Y., Nanver, L.K., Schellevis, H.

“…A solid-phase epitaxy (SPE) process based on material inversion of an amorphous silicon (alpha-Si) on aluminum layer-stack is applied to form ultrashallow…”
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3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps by Guo, W., Van Der Plas, G., Ivankovic, A., Eneman, G., Cherman, V., De Wachter, B., Mercha, A., Gonzalez, M., Civale, Y., Redolfi, A., Buisson, T., Jourdan, A., Vandevelde, B., Rebibis, K. J., De Wolf, I., La Manna, A., Beyer, G., Beyne, E., Swinnen, B.

“…The 3D IC stacking technology with Through Silicon via (TSV) approach promises lower cost, smaller footprint and higher performance for heterogeneous system…”
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1.9 nm wide ultra-high aspect-ratio bulk-Si FinFETs by Jovanovic, V., Poljak, M., Suligoj, T., Civale, Y., Nanver, L.K.

“…This work focuses on FinFETs with high aspect-ratio and thus a wide MOSFET channels in each fin, which translates into higher device density per chip area and…”
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Interposer technology for high band width interconnect applications by Detalle, Mikael, La Manna, A., De Vos, J., Nolmans, P., Daily, R., Civale, Y., Beyer, G., Beyne, E.

“…Silicon Interposer provides very high density interconnect combining through Silicon vias and fine wiring. The concept reported in this paper is implementing…”
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Electrical characterization method to study barrier integrity in 3D through-silicon vias by Li, Y.-L, Velenis, D., Kauerauf, T., Stucchi, M., Civale, Y., Redolfi, A., Croes, K.

“…In this paper, the controlled I-V (IV ctrl ) method is adopted for the barrier integrity characterization of TSVs at wafer level. Planar capacitor structures…”
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Novel seed layer formation using direct electroless copper deposition on ALD-Ru layer for high aspect ratio TSV by Inoue, F., Philipsen, H., Radisic, A., Armini, S., Civale, Y., Leunissen, P., Shingubara, S.

“…High aspect ratio through-Si vias (2 μmφ, AR 15) have been filled without voids on coupon scale by using an electroless deposited Cu seed layer on ALD-Ru. The…”
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