Search Results - "Cintra, Marcelo"

ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging by Joshi, Arpit, Nagarajan, Vijay, Viglas, Stratis, Cintra, Marcelo

“…Non-volatile memory (NVM) is emerging as a fast byte-addressable alternative for storing persistent data. Ensuring atomic durability in NVM requires logging…”
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DHTM: Durable Hardware Transactional Memory by Joshi, Arpit, Nagarajan, Vijay, Cintra, Marcelo, Viglas, Stratis

“…The emergence of byte-addressable persistent (non-volatile) memory provides a low latency and high bandwidth path to durability. However, programmers need…”
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Efficient persist barriers for multicores by Joshi, Arpit, Nagarajan, Vijay, Cintra, Marcelo, Viglas, Stratis

“…Emerging non-volatile memory technologies enable fast, fine-grained persistence compared to slow block-based devices. In order to ensure consistency of…”
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Generating code for holistic query evaluation by Krikellas, Konstantinos, Viglas, Stratis D, Cintra, Marcelo

“…We present the application of customized code generation to database query evaluation. The idea is to use a collection of highly efficient code templates and…”
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An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs by Fensch, Christian, Cintra, Marcelo

“…The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these…”
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Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses by Ros, Alberto, Xekalakis, Polychronis, Cintra, Marcelo, Acacio, Manuel E., Garcia, Jose M.

“…The design of cache memories is a crucial part of the design cycle of a modern processor, since they are able to bridge the performance gap between the…”
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Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters by Ashby, T J, Díaz, Pedro, Cintra, M

“…Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves…”
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Just-in-Time Compilation Techniques for Hardware/Software Co-Designed Processors by Cintra, Marcelo

“…Recently, with the broad adoption of mobile devices, considerable research efforts have concentrated on innovative dynamic optimization techniques to improve…”
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Handling branches in TLS systems with Multi-Path Execution by Xekalakis, Polychronis, Cintra, Marcelo

“…Thread-Level Speculation (TLS) has been proposed to facilitate the extraction of parallel threads from sequential applications. Most prior work on TLS has…”
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Complementing user-level coarse-grain parallelism with implicit speculative parallelism by Ioannou, Nikolas, Cintra, Marcelo

“…Multi-core and many-core systems are the norm in contemporary processor technology and are expected to remain so for the foreseeable future. Programs using…”
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An OS-based alternative to full hardware coherence on tiled CMPs by Fensch, C., Cintra, M.

“…The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these…”
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Automatic Skleton-Driven Memory Affinity for Transactional Worklist Applications by Fabrício Góes, Luís, Pousa Ribeiro, Christiane, Bastos Castro, Marcio, Mehaut, Jean-François, Cole, Murray, Cintra, Marcelo

“…Memory affinity has become a key element to achieve scalable performance on multi-core platforms. Mechanisms such as thread scheduling, page allocation and…”
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Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer by Ioannou, N., Kauschke, M., Gries, M., Cintra, M.

“…To improve energy efficiency processors allow for Dynamic Voltage and Frequency Scaling (DVFS), which enables changing their performance and power consumption…”
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Design space exploration of a software speculative parallelization scheme by Cintra, M., Llanos, D.R.

“…With speculative parallelization, code sections that cannot be fully analyzed by the compiler are optimistically executed in parallel. Hardware schemes are…”
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Autotuning Skeleton-Driven Optimizations for Transactional Worklist Applications by goes, Luıs Fabrıcio Wanderley, Ioannou, N., Xekalakis, P., Cole, M., Cintra, M.

“…Skeleton or pattern-based programming allows parallel programs to be expressed as specialized instances of generic communication and computation patterns. In…”
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Automatic Skeleton-Driven Memory Affinity for Transactional Worklist Applications by Góes, Luís Fabrício Wanderley, Ribeiro, Christiane Pousa, Castro, Márcio, Méhaut, Jean-François, Cole, Murray, Cintra, Marcelo

“…Memory affinity has become a key element to achieve scalable performance on multi-core platforms. Mechanisms such as thread scheduling, page allocation and…”
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A machine learning-based approach for thread mapping on transactional memory applications by Castro, M., Goes, L. F. W., Ribeiro, C. P., Cole, M., Cintra, M., Mehaut, J-F

“…Thread mapping has been extensively used as a technique to efficiently exploit memory hierarchy on modern chip-multiprocessors. It places threads on cores in…”
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Increasing the energy efficiency of TLS systems using intermediate checkpointing by Khan, S., Ioannou, N., Xekalakis, P., Cintra, M.

“…With the advent of Chip Multiprocessors (CMPs), improving performance relies on the programmers/compilers to expose thread level parallelism to the underlying…”
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CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors by Porpodas, Vasileios, Cintra, Marcelo

“…Clustered architectures have been proposed as a solution to the scalability problem of wide ILP processors. VLIW architectures, being wide-issue by design,…”
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Distance-aware round-robin mapping for large NUCA caches by Ros, A., Cintra, M., Acacio, M.E., Garcia, J.M.

“…In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to…”
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