Search Results - "Chulsoon Chang"

  • Showing 1 - 6 results of 6
Refine Results
  1. 1
    A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

    A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ by Lee, Daewoong, Baek, Jaehyeok, Kwon, Hye-Jung, Kwon, Dae-Hyun, Cho, Chulhee, Kim, Sang-Hoon, An, Donggun, Chang, Chulsoon, Lim, Unhak, Im, Jiyeon, Sung, Wonju, Kim, Hye-Ran, Park, Sun-Young, Kim, Hyoung-Joo, Seol, Hoseok, Kim, Juhwan, Shin, Jungbum, Kang, Gil-Young, Kim, Yong-Hun, Kim, Sooyoung, Park, Wansoo, Kim, Seok-Jung, Lee, Chan-Yong, Lee, Seungseob, Park, Tae-Hoon, Oh, Chi-Sung, Ban, Hyodong, Ko, Hyungjong, Song, Hoyoung, Oh, Tae-Young, Hwang, Sang-Joon, Oh, Kyung-Suk, Choi, Jung-Hwan, Lee, Jooyoung

    Published in IEEE journal of solid-state circuits (01-01-2023)
    “…This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter…”
    Get full text
    Journal Article
    Save to List
    Saved in:
  2. 2
    A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

    A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus by Lee, Daewoong, Kwon, Hye-Jung, Kwon, Daehyun, Baek, Jaehyeok, Cho, Chulhee, Kim, Sanghoon, An, Donggun, Chang, Chulsoon, Lim, Unhak, Im, Jiyeon, Sung, Wonju, Kim, Hye-Ran, Park, Sun-Young, Kim, HyoungJoo, Seol, Hoseok, Kim, Juhwan, Shin, Junabum, Kang, Kil-Youna, Kim, Yona-Hun, Kim, Sooyoung, Park, Wansoo, Kim, Seok-Jung, Lee, Chanyong, Lee, Seungseob, Park, TaeHoon, Oh, ChiSung, Ban, Hyodong, Ko, Hyungjong, Song, Hoyoung, Oh, Tae-Young, Hwang, SangJoon, Oh, Kyung Suk, Choi, JungHwan, Lee, Jooyoung

    “…Graphic DRAMs have been developed to increase maximum I/O interface speeds to satisfy the demand of high-performance graphic applications [1]-[5]. Recently,…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  3. 3
    65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications

    65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications by Hoon Lim, Soon-Moon Jung, Youngseop Rah, Taehong Ha, Hanbyung Park, Chulsoon Chang, Wonsuk Cho, Jaikyun Park, Byoungkeun Son, Jaehun Jeong, Hoosung Cho, Bonghyun Choi, Kinam Kim

    “…For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  4. 4
    Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

    Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications by Soon-Moon Jung, Youngseop Rah, Taehong Ha, Hanbyung Park, Chulsoon Chang, Seungchul Lee, Jongho Yun, Wonsuk Cho, Hoon Lim, Jaikyun Park, Jaehun Jeong, Byoungkeun Son, Jaehoon Jang, Bonghyun Choi, Hoosung Cho, Kinam Kim

    “…In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell,…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  5. 5
    A novel 0.79 /spl mu/m/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM

    A novel 0.79 /spl mu/m/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM by Soon-Moon Jung, Hyungshin Kwon, Jaehun Jeong, Wonseok Cho, Sungbong Kim, Hoon Lim, Kwangok Koh, Youngseop Rah, Jaekyun Park, Heesoo Kang, Gyuho Lyu, Joonbum Park, Chulsoon Chang, Youngchul Jang, Donggun Park, Kinam Kim, Moon Yong Lee

    “…The smallest SRAM cell, 0.79 /spl mu/m/sup 2/, was realized by a revolutionary cell layout, fine tuned OPC technique to overcome the 248 nm KrF lithography…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  6. 6
    A novel 0.79μm2 SRAM cell by KrF lithography and high performance 90nm CMOS technology for ultra high speed SRAM

    A novel 0.79μm2 SRAM cell by KrF lithography and high performance 90nm CMOS technology for ultra high speed SRAM by JUNG, Soon-Moon, KWON, Hyungshin, LYU, Gyuho, PARK, Joonbum, CHANG, Chulsoon, JANG, Youngchul, PARK, Donggun, KIM, Kinam, MOON YONG LEE, JEONG, Jaehun, CHO, Wonseok, KIM, Sungbong, LIM, Hoon, KOH, Kwangok, RAH, Youngseop, PARK, Jaekyun, KANG, Heesoo

    Published 2002
    Get full text
    Conference Proceeding
    Save to List
    Saved in:

Search Tools: