Search Results - "Chou, Eric Y."

Developments in nano/giga systems: Nanometer mixed-signal system-on-a-chip design by Chou, Eric Y, Sheu, Bing

“…A mixed-signal system-on-a-chip (SoC) design methodology and the supporting CAD tools are presented. A known tool set is identified for illustration purposes…”
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A compact neural network for partial-response maximum-likelihood detectors: algorithmic study by Chou, E.Y., Sheu, B.J., Wang, M.Y.

“…A compact neural network algorithm for partial-response maximum-likelihood (PRML) sequence detection is presented. Compact neural networks are a class of…”
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Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture by Chou, Eric Y., Budrys, A. J., Cham, Kit M.

“…CMOS image sensors are very suitable for battery-operated camera systems due to their low power nature. In this research work, a salient integration mode CMOS…”
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A compact neural network for VLSI PRML detectors: scalable architecture by Chou, E.Y., Sheu, B.J., Wang, M.Y.

“…Very large scale integration (VLSI) compact neural network architecture for maximum-likelihood detector of partial response (PR) communication receivers is…”
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Baud-rate channel equalization in nanometer technologies : Nanoelectronic circuits and systems by CHOU, Eric Y, HUANG, Jamie C, HUANG, Maggie S, HSIEH, Mark C, HSU, Andrew Y

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VLSI design of optimization and image processing cellular neural networks by Chou, E.Y., Sheu, B.J., Chang, R.C.

“…Detailed design of a current-mode cellular neural network for optimization and image processing is presented. The hardware annealing function is also embedded…”
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A hardware annealing method for optimal solutions on cellular neural networks by Bang, S.H., Sheu, B.J., Chou, E.Y.

“…An engineering annealing method, called hardware annealing, for optimal solutions on cellular neural networks is presented. Cellular neural networks have great…”
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A state-constrained model for cellular nonlinear network optimization by Chou, E.Y., Sheu, B.J., Tsai, R.H.

“…A G/sub m/C-style state constrained neuron (SCN) model for the design of processors in analog recurrent neural networks such as Hopfield neural networks,…”
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Baud-rate channel equalization in nanometer technologies by Chou, E.Y., Huang, J.C., Huang, M.S., Hsieh, M.C., Hsu, A.Y.

“…Chip design technology has been accelerating the advances of the communication technology in the past decades because a chip with larger computing capacity can…”
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System-on-a-chip design for modern communications by Chou, E.Y., Bing Sheu

“…In this article, the trends and opportunities in SoC IC design for the networking communication industry is presented. These trends will significantly affect…”
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Behavioral simulation of densely-connected analog cellular array processors for high-performance computing by Wu, Tony H., Sheu, Bing J., Chou, Eric Y.

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