Search Results - "Chopra, Kaviraj"

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors by Rao, R.R., Chopra, K., Blaauw, D.T., Sylvester, D.M.

“…Soft errors have emerged as an important reliability challenge for nanoscale very large scale integration designs. In this paper, we present a fast and…”
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Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques by Veetil, V, Chopra, K, Blaauw, D, Sylvester, D

“…In this paper, we propose a stratification+hybrid quasi Monte Carlo (SH-QMC) approach to improve the efficiency of Monte Carlo-based statistical static timing…”
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Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States by Chopra, K., Vrudhula, S.

“…Static power consumption due to subthreshold, gate, and junction leakages has become a significant component of the total power consumption. For nanoscale…”
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Circuit optimization using statistical static timing analysis by Agarwal, Aseem, Chopra, Kaviraj, Blaauw, David, Zolotov, Vladimir

“…In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay…”
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Statistical Timing Analysis: From Basic Principles to State of the Art by Blaauw, D., Chopra, K., Srivastava, A., Scheffer, L.

“…Static-timing analysis (STA) has been one of the most pervasive and successful analysis engines in the design of digital circuits for the last 20 years…”
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Analysis and Modeling of CD Variation for Statistical Static Timing by Cline, B., Chopra, K., Blaauw, D., Yu Cao

“…Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much…”
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A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis by Chopra, K., Zhai, B., Blaauw, D., Sylvester, D.

“…Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability…”
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Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis by Cheng Zhuo, Chopra, K., Sylvester, D., Blaauw, D.

“…Gate oxide breakdown (OBD) is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip OBD…”
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Victim Alignment in Crosstalk-Aware Timing Analysis by Gandikota, Ravikishore, Chopra, Kaviraj, Blaauw, David, Sylvester, Dennis

“…Modeling the effect of coupling-noise on circuit delay is a key issue in static timing analysis and involves the victim-aggressor alignment problem. As…”
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A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance by Srivastava, A., Chopra, K., Shah, S., Sylvester, D., Blaauw, D.

“…Increasing levels of process variation in current technologies have a major impact on power and performance and result in parametric yield loss. In this paper,…”
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Statistical performance analysis and optimization of digital circuits by Chopra, Kaviraj

“…Aggressive device scaling has made it imperative to account for process variations in the design flow. A robust model of process variations is an essential…”
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An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits by Rao, R.R., Chopra, K., Blaauw, D., Sylvester, D.

“…Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER)…”
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Statistical Timing Based Optimization using Gate Sizing by Agarwal, Aseem, Chopra, Kaviraj, Blaauw, David

“…The increased dominance of intra-die process variations has motivated the field of Statistical Static Timing Analysis (SSTA) and has raised the need for…”
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Transistor-Specific Delay Modeling for SSTA by Cline, B., Chopra, K., Blaauw, D., Torres, A., Sundareswaran, S.

“…SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying…”
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CAD tools for variation tolerance by Blaauw, David, Chopra, Kaviraj

“…Process variability greatly affects power and timing of nanometer scale CMOS circuits, leading to parametric yield loss due to both timing and power constraint…”
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Top-k aggressors sets in delay noise analysis by Gandikota, Ravikishore, Chopra, Kaviraj, Blaauw, David, Sylvester, Dennis, Becer, Murat

“…We present, in this paper, novel algorithms to compute the set of "top-k" aggressors in a design. We show that the computation of the set of top-k aggressors…”
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Implicit pseudo boolean enumeration algorithms for input vector control by Chopra, Kaviraj, Vrudhula, Sarma B. K.

“…In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new…”
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A framework for battery-aware sensor management by Dasika, S., Vrudhula, S., Chopra, K., Srinivasan, R.

“…A distributed sensor network (DSN) designed to cover a given region R, is said to be alive if there is at least one subset of sensors that can collectively…”
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A statistical approach for full-chip gate-oxide reliability analysis by Chopra, Kaviraj, Zhuo, Cheng, Blaauw, David, Sylvester, Dennis

“…Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide…”
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Statistical Timing Based Optimization using Gate Sizing by Agarwal, Aseem, Chopra, Kaviraj, Blaauw, David

“…Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005) The increased dominance of intra-die process variations has motivated the field…”
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