Search Results - "Chixiao Chen"

Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing by Aili Wang, Chixiao Chen, Shi, Chuanjin Richard

“…This paper presents the design and analysis of an always-ON comparator capable of detecting mV-range input voltage signals reliably with sub-nW power…”
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A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1 by Wang, Zhenyu, Wang, Mingshuo, Gu, Weiru, Chen, Chixiao, Ye, Fan, Ren, Junyan

“…This paper presents a power-efficient, high-linearity pipelined ADC, utilizing a combined front-end of the sample/hold circuit (S/H) and the first multiplying…”
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iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric by Chen, Chixiao, Liu, Xindi, Peng, Huwan, Ding, Hongwei, Richard Shi, C.-J.

“…This paper presents iFPNA, instruction-and-fabric programmable neuron array: a deep learning processor using a neural network specific instruction set…”
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An ARMA-Model-Based NTF Estimation on Continuous-Time \Delta\Sigma Modulators by Chen, Chixiao, Feng, Zemin, Xu, Jun, Ye, Fan, Ren, Junyan

“…In this brief, a noise transfer function (NTF) estimation algorithm is developed for continuous-time delta-sigma modulators. Different from previous methods,…”
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High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators by Hang Hu, Zemin Feng, Chixiao Chen, Fan Ye, Junyan Ren

“…In this paper, a high speed digital excess loop delay (ELD) compensation scheme with hybrid thermometer coding is proposed. In this high speed compensation,…”
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A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method by Zemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu, Junyan Ren

“…This paper presents a 3 rd -order continuous time sigma-delta (ΣΔ) modulator (CTSDM) using several low power techniques. A compact architecture of 3rd-order…”
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100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array by Wang Jingjing, Xu Rongjin, Chen Chixiao, Ye Fan, Xu Jun, Ren Junyan

“…This paper presents a low power 9-bit 100MS/s successive approximation register analog-to-digital converter (SAR ADC) due to the custom capacitor array. In…”
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A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators by Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren

“…A 400-MS/s 8-b SAR ADC with 2-b/cycle conversion is presented in this paper. Compared with conventional SAR structure, an AUX-DAC is proposed to achieve high…”
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A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system by Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren

“…This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock…”
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A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier by Chixiao Chen, Zemin Feng, Huabin Chen, Mingshuo Wang, Jun Xu, Fan Ye, Junyan Ren

“…This paper presents a new low offset comparator with a mismatch-suppressed dynamic preamplifier Various mismatches contribute to comparators's input referred…”
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Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers by Fan Jiang, Chixiao Chen, Yuzhong Xiao, Jun Xu, Junyan Ren

“…Currently, less-than-one-cycle loop delay is the key factor to impede higher clock rate and wide bandwidth continuous-time oversampling modulators. In this…”
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A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique by Yongzhen Chen, Chixiao Chen, Qiang Zhang, Ye Fan, Junyan Ren

“…A CMOS fully differential high gain-bandwidth (GBW) operational amplifier applied in a sample-and-hold (S&H) circuit is presented in the paper. High bandwidth…”
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A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator by Zemin Feng, Chixiao Chen, Ye Fan, Jun Xu, Junyan Ren

“…Finite gain-bandwidth (GBW) effects include gain-error (GE) and loop delay which would degrade the overall performance of continuous-time ΣΔ modulator (CTDSM)…”
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A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers by Yuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren

“…A third-order multi-bit feedforward-feedback (FF-FB) mixed continuous time sigma-delta modulator (CTSDM) for WLAN receivers is presented. The comparators and…”
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An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling by Chixiao Chen, ShengChang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren

“…A sampling switch with an embedded Digital-to-Skew Converter (DSC) is presented in this paper. The proposed switch eliminates time-interleaved ADCs' skews by…”
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A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application by Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yujing Lin, Ning Li, Junyan Ren

“…This paper presents a 4-channel 8-bit 6-2 segmented current-steering digital-to-analog converter implemented in 0.13μm CMOS process. For the consideration of…”
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Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS by Xiaolong Liu, Chixiao Chen, Junyan Ren, Luong, Howard C.

“…This paper presents a transformer-based magnetic-tuning technique to achieve wide frequency tuning range and low power consumption for W-band oscillators…”
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Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering by Wu, Lizhou, Zhu, Haozhe, Zheng, Jiapei, Li, Mengjie, Cheng, Yinuo, Liu, Qi, Zeng, Xiaoyang, Chen, Chixiao

“…Neural radiance field (NeRF) has proved to be promising in augmented/virtual-reality applications. However, the deployment of NeRF on edge devices suffers from…”
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A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration by Yang, Yinglin, Wang, Yunzhengmao, Yi, Tengyue, Chen, Chixiao, Liu, Qi

“…This work presents an agilely designed high-speed energy-efficient Die-to-Die interconnect PHY for silicon interposer based 2.5D integration. Due to the…”
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Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning by Zhu, Haozhe, Zhang, Hongyi, He, Siqi, Li, Mengjie, Zeng, Xiaoyang, Chen, Chixiao

“…With the massive data transfer of deep neural network (DNN) models hindering their employment in energy-stringent scenarios, compute-in-memory (CIM)…”
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