Search Results - "Chinnery, D. G."

Linear programming for sizing, Vth and Vdd assignment by Chinnery, D. G., Keutzer, K.

“…Most circuit sizing tools calculate the tradeoff between each gate's delay and power or area, and then greedily change the gate with the best tradeoff. We show…”
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Closing the gap between ASIC and custom: an ASIC perspective by Chinnery, D. G., Keutzer, K.

“…We investigate the differences in speed between application-specific integrated circuits and custom integrated circuits when each are implemented in the same…”
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Closing the power gap between ASIC and custom: an ASIC perspective by Chinnery, D. G., Keutzer, K.

“…We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um…”
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Achieving 550 MHz in an ASIC methodology by Chinnery, D. G., Nikolic, B., Keutzer, K.

“…Typically, good automated ASIC designs may be two to five times slower than handcrafted custom designs. At last year's DAC this was examined and causes of the…”
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A functional validation technique: biased-random simulation guided by observability-based coverage by Tasiran, S., Fallah, F., Chinnery, D.G., Weber, S.J., Keutzer, K.

“…We present a simulation-based semi-formal verification method for sequential circuits described at the register-transfer level. The method consists of an…”
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