Search Results - "Ching-Fa Yeh"
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1
Post-Cu CMP cleaning for colloidal silica abrasive removal
Published in Microelectronic engineering (01-11-2004)“…In this study, an efficient approach for the removal of colloidal silica abrasives from the polished copper surface was proposed and demonstrated. This…”
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2
Electrical Characteristics of the HfAlON Gate Dielectric With Interfacial UV-Ozone Oxide
Published in IEEE electron device letters (01-01-2008)“…In this letter, the electrical properties of a HfAlON dielectric with UV-O 3 interfacial oxide were comprehensively studied and then compared with those of a…”
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3
Nonvolatile memory characteristics of nickel-silicon-nitride nanocrystal
Published in Applied physics letters (20-08-2007)“…The formation of nickel-silicon-nitride nanocrystals by sputtering a comixed target in the argon and nitrogen environment is proposed in this letter. High…”
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4
Novel post CMP cleaning using buffered HF solution and ozone water
Published in Applied surface science (30-06-2003)“…Post chemical mechanical polishing (CMP) cleaning is a key process for copper (Cu) CMP in dual damascene interconnection technology. During the post CMP…”
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Journal Article Conference Proceeding -
5
Influence of measuring environment on the electrical characteristics of pentacene-based thin film transistors
Published in Thin solid films (22-11-2004)“…This work concerns the electrical properties and carrier transport behavior of polycrystalline pentacene-based thin film transistors (TFTs) in air and…”
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6
Investigation of grain boundary control in the drain junction on laser-crystalized poly-Si thin film transistors
Published in IEEE electron device letters (01-07-2003)“…This letter investigates the influences of grain boundaries in the drain junction on the performance and reliability of laser-crystalized poly-Si thin film…”
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7
Device Transfer Technology by Backside Etching (DTBE) for Poly-Si Thin-Film Transistors on Glass/Plastic Substrate
Published in Japanese Journal of Applied Physics (15-09-2003)Get full text
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8
The removal of airborne molecular contamination in cleanroom using PTFE and chemical filters
Published in IEEE transactions on semiconductor manufacturing (01-05-2004)“…Cleanroom contamination and its impact on the performance of devices are beginning to be investigated due to the increasing sensitivity of the semiconductor…”
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9
Impact of Air Filter Material on Metal Oxide Semiconductor (MOS) Device Characteristics in HF Vapor Environment
Published in Japanese Journal of Applied Physics (15-05-2004)“…Airborne molecular contamination (AMC) is becoming increasingly important as devices are scaled down to the nanometer generation. Optimum ultra low penetration…”
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10
A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition
Published in IEEE electron device letters (01-08-1999)“…We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFT's)…”
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11
Effects of mechanical characteristics on the chemical-mechanical polishing of dielectric thin films
Published in Thin solid films (15-12-1996)“…The effects of as-deposited (intrinsic) stress, externally applied (extrinsic) stresses, hardness, and modulus of various dielectric films on…”
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12
The effect of temperature on I-V characteristics of a Si:H photodiode
Published in Japanese Journal of Applied Physics (01-09-1992)“…A 16-bit/mm, high-resolution, Schottky a-Si:H photodiode linear sensor array was fabricated, and the effect of temperature on its I-V characteristics was…”
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13
Novel contact hole fabrication using selective liquid-phase deposition instead of reactive ion etching
Published in IEEE electron device letters (01-01-1999)“…This work forms a contact hole utilizing the selectively liquid-phase deposited (S-LPD) silicon-oxide technique instead of the conventional reactive ion…”
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14
Application of plasma immersion ion implantation doping to low-temperature processed poly-Si TFTs
Published in IEEE electron device letters (01-11-1998)“…This work applied, for the first time, plasma immersion ion implantation (PIII) for source/drain doping on low-temperature processed polysilicon thin-film…”
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15
Effects of plasma treatment on the properties of room-temperature liquid-phase deposited (LPD) oxide films
Published in Journal of non-crystalline solids (01-07-1995)“…Effects of plasma treatment including H 2 or O 2 on the properties of LPD oxide were investigated. After plasma treatment, the physicochemical characteristics…”
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Journal Article Conference Proceeding -
16
Novel Sidewall Capping for Degradation-Free Damascene Trenches of Low-Permittivity Methylsilsesquioxane
Published in Japanese Journal of Applied Physics (01-04-2000)“…A low-permittivity organic dielectric, methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in…”
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17
Improved I-V characteristics of polysilicon thin film transistors with novel dual-buffer drain structure
Published in Japanese Journal of Applied Physics (1994)“…ON/OFF current ratio of poly-Si TFTs has been improved by using a novel structure called the dual-buffer drain (DBD). The new DBD TFT not only reduces the…”
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18
Thinner liquid phase deposited oxide for polysilicon thin-film transistors
Published in IEEE electron device letters (01-11-1995)“…To scale down the gate insulator thickness of polysilicon thin-film transistors (poly-Si TFT's), a thinner oxide is developed by liquid-phase deposition with a…”
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19
Chemical mechanical polishing of PSG and BPSG dielectric films: the effect of phosphorus and boron concentration
Published in Thin solid films (01-12-1995)“…Chemical-mechanical polishing of blanket and patterned oxide films doped with phosphorus and boron has been studied. FTIR was used to characterize the film…”
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Journal Article Conference Proceeding -
20
Novel gate dielectric films formed by ion plating for low-temperature-processed polysilicon TFTs
Published in IEEE electron device letters (01-09-1996)“…A novel SiO/sub 2/ film formed by ion plating (IP) at room temperature was developed for low-temperature-processed (LTP) (<625/spl deg/C) polysilicon thin-film…”
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