Search Results - "Chiarella, Thomas"

Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs by Tyaginov, Stanislav, O’Sullivan, Barry, Chasin, Adrian, Rawal, Yaksh, Chiarella, Thomas, de Carvalho Cavalcante, Camila Toledo, Kimura, Yosuke, Vandemaele, Michiel, Ritzenthaler, Romain, Mitard, Jerome, Palayam, Senthil Vadakupudhu, Reifsnider, Jason, Kaczer, Ben

“…We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected…”
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A Pragmatic Model to Predict Future Device Aging by Brown, James, Tok, Kean H., Gao, Rui, Ji, Zhigang, Zhang, Weidong, Marsland, John S., Chiarella, Thomas, Franco, Jacopo, Kaczer, Ben, Linten, Dimitri, Zhang, Jian F.

“…To predict long term device aging under use bias, models extracted from voltage accelerated tests must be extrapolated into the future. The traditional model…”
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Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET by Kim, Soohyun, Kim, Jungchun, Jang, Doyoung, Ritzenthaler, Romain, Parvais, Bertrand, Mitard, Jerome, Mertens, Hans, Chiarella, Thomas, Horiguchi, Naoto, Lee, Jae Woo

“…The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are…”
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Mobility analysis of surface roughness scattering in FinFET devices by Lee, Jae Woo, Jang, Doyoung, Mouis, Mireille, Kim, Gyu Tae, Chiarella, Thomas, Hoffmann, Thomas, Ghibaudo, Gérard

“…► Mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. ► The sidewall and top surface drain current…”
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Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis by Bhoir, Mandar S., Chiarella, Thomas, Ragnarsson, Lars Ake, Mitard, Jerome, Terzeiva, Valentina, Horiguchi, Naoto, Mohapatra, Nihar R.

“…This paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance and variability of FinFETs. It is observed through detailed…”
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Sidewall Crystalline Orientation Effect of Post-treatments for a Replacement Metal Gate Bulk Fin Field Effect Transistor by Lee, Jae Woo, Simoen, Eddy, Veloso, Anabela, Cho, Moon Ju, Boccardi, Guillaume, Ragnarsson, Lars-Åke, Chiarella, Thomas, Horiguchi, Naoto, Groeseneken, Guido, Thean, Aaron

“…The crystalline orientation effect is investigated for post-treatments of a replacement metal gate (RMG) p-type bulk fin field effect transistor (FinFET)…”
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Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme by Veloso, Anabela, Boccardi, Guillaume, Ragnarsson, Lars-Åke, Higuchi, Yuichi, Arimura, Hiroaki, Lee, Jae Woo, Simoen, Eddy, Cho, Moon Ju, Roussel, Philippe J., Paraschiv, Vasile, Shi, Xiaoping, Schram, Tom, Chew, Soon Aik, Brus, Stephan, Dangol, Anish, Vecchio, Emma, Sebaai, Farid, Kellens, Kristof, Heylen, Nancy, Devriendt, Katia, Dekkers, Harold, Van Ammel, Annemie, Witters, Thomas, Conard, Thierry, Vaesen, Inge, Richard, Olivier, Bender, Hugo, Athimulam, Raja, Chiarella, Thomas, Thean, Aaron, Horiguchi, Naoto

“…We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices,…”
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Boron Triiodide-Mediated Reduction of Nitroarenes Using Borohydride Reagents by Ćorković, Andrej, Chiarella, Thomas, Williams, Florence J.

“…The reduction of nitroarenes using KBH4 and I2 is described. BI3 is generated in situ and was shown to be the active reductant. Conditions were optimized for…”
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Investigation of Dielectric and Quantum Confinement Based Dopant Deactivation in the Extension Region of FinFET by Saurabh, Nishant, Patil, Shubham, Rawat, Amita, Chiarella, Thomas, Parvais, Bertrand, Ganguly, Udayan

“…Spacers with low dielectric constant have been significantly explored in the literature to reduce delay due to the parasitic capacitance. However, it…”
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ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy by Chen, Wen-Chieh, Chen, Shih-Hung, Chiarella, Thomas, Hellings, Geert, Linten, Dimitri, Groeseneken, Guido

“…In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are…”
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Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies by Rawat, Amita, Sharan, Neha, Jang, Doyoung, Chiarella, Thomas, Bufler, Fabian M., Catthoor, Francky, Parvais, Bertrand, Ganguly, Udayan

“…We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework-enabling the estimation of performance…”
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V ₜ Extraction Methodologies Influence Process Induced V ₜ Variability: Does This Fact Still Hold for Advanced Technology Nodes? by Bhoir, Mandar S., Chiarella, Thomas, Mitard, Jerome, Horiguchi, Naoto, Mohapatra, Nihar Ranjan

“…In this work, we have investigated the influence of [Formula Omitted] extraction procedure on overall [Formula Omitted] variability of sub-10 nm [Formula…”
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Vₜ Extraction Methodologies Influence Process Induced Vₜ Variability: Does This Fact Still Hold for Advanced Technology Nodes? by Bhoir, Mandar S., Chiarella, Thomas, Mitard, Jerome, Horiguchi, Naoto, Mohapatra, Nihar Ranjan

“…In this work, we have investigated the influence of <inline-formula> <tex-math notation="LaTeX">{V}_{\text {t}} </tex-math></inline-formula> extraction…”
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Channel Hot Carrier Degradation Mechanism in Long/Short Channel n-FinFETs by Moonju Cho, Roussel, Philippe, Kaczer, Ben, Degraeve, Robin, Franco, Jacopo, Aoulaiche, Marc, Chiarella, Thomas, Kauerauf, Thomas, Horiguchi, Naoto, Groeseneken, Guido

“…The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades…”
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Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle by Vincent, Benjamin, Hathwar, Raghu, Kamon, Mattan, Ervin, Joseph, Schram, Tom, Chiarella, Thomas, Demuynck, Steven, Baudot, Sylvain, Siew, Yong Kong, Kubicek, Stenfan, Litta, Eugenio Dentoni, Chew, SoonAik, Mitard, Jerome

“…A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device…”
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Extraction of the Random Component of Time-Dependent Variability Using Matched Pairs by Kaczer, Ben, Franco, Jacopo, Roussel, Philippe J., Groeseneken, Guido, Chiarella, Thomas, Horiguchi, Naoto, Grasser, Tibor

“…Based on the so-called defect-centric statistics, we propose the average impact of a single charged trap on FET threshold voltage as a physically based measure…”
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Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs by Eyben, Pierre, De Keersgieter, An, Matagne, Philippe, Chiarella, Thomas, Porret, Clément, Hikavyy, Andriy, Siew, Yong Kong, Goux, Ludovic, Mitard, Jérôme, Horiguchi, Naoto

“…Abstract In this paper we present an extended analysis of thsse impact of SiGe p-epi source/drain engineering on sub-20 nm gate length p-FinFETs performance…”
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The Improvement of Subthreshold Slope and Transconductance of p-Type Bulk Si Field-Effect Transistors by Solid-Source Doping by Kikuchi, Yoshiaki, Chiarella, Thomas, De Roest, David, Kenis, Karine, Ong, Patrick, Horiguchi, Naoto

“…As dimension of bulk Si field-effect transistors scales down, novel techniques for impurity profile design at channel area are required because suppression of…”
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Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field by Toledano-Luque, Maria, Matagne, Philippe, Sibaja-Hernandez, Arturo, Chiarella, Thomas, Ragnarsson, Lars-Ake, Soree, Bart, Cho, Moonju, Mocuta, Anda, Thean, Aaron

“…Superior reliability of junctionless (JL) compared with inversion-mode field-effect transistors (FETs) is experimentally demonstrated on bulk FinFET wafers…”
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Plasma doping and reduced crystalline damage for conformally doped fin field effect transistors by Woo Lee, Jae, Sasaki, Yuichiro, Ju Cho, Moon, Togo, Mitsuhiro, Boccardi, Guillaume, Ritzenthaler, Romain, Eneman, Geert, Chiarella, Thomas, Brus, Stephan, Horiguchi, Naoto, Groeseneken, Guido, Thean, Aaron

“…Low frequency noise and hot carrier reliability analysis of the plasma doping scheme are investigated for advanced fin field effect transistor (FinFET)…”
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