Search Results - "Chenson Chen"
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1
A wafer-scale 3-D circuit integration technology
Published in IEEE transactions on electron devices (01-10-2006)“…The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D…”
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Journal Article -
2
Radiation Effects in 3D Integrated SOI SRAM Circuits
Published in IEEE transactions on nuclear science (01-12-2011)“…Radiation effects are presented for the first time for vertically integrated 3 × 64-kb SOI SRAM circuits fabricated using the 3D process developed at MIT…”
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Journal Article -
3
SET Characterization in Logic Circuits Fabricated in a 3DIC Technology
Published in IEEE transactions on nuclear science (01-12-2011)“…Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are…”
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Journal Article -
4
SOI for MEMS and advanced packaging
Published in 2012 IEEE International SOI Conference (SOI) (01-10-2012)“…Silicon on Insulator (SOI) Technologies offer many advantages for the fabrication and advanced packaging of MEMS and IC devices and systems. The buried oxide…”
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Conference Proceeding -
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SOI circuits powered by embedded solar cell
Published in IEEE 2011 International SOI Conference (01-10-2011)“…Solar cells embedded in the SOI substrate were successfully used as the sole energy source to power a ring oscillator fabricated using an ultra-low-power fully…”
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Conference Proceeding -
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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)“…A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2…”
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Conference Proceeding -
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Enhanced resolution for future fabrication
Published in IEEE circuits and devices magazine (01-01-2003)“…We have developed resolution-enhanced optical lithography processes that have enabled us to fabricate devices with deep sub-100 nm feature sizes. Isolated gate…”
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Journal Article