CISPR 25 Conducted Emission Simulation and Measurement Correlation of an Automotive Isolated Solid-State Relay

CISPR 25 Conducted Emission Simulation and Measurement Correlation of an Automotive Isolated Solid-State Relay

Isolator integrated circuits (ICs) that employ AC switching to send power or data across magnetic or capacitive insulation barriers can create excessive transient di/dt and dv/dt loops that exacerbate electromagnetic emissions. In this work, we developed a robust system-level coupled circuit-to-elec...

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Bibliographic Details
Published in:2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) pp. 1 - 3
Main Authors: Chen, Jie, Murugan, Rajen, Broze, John, Kittur, Premsagar, Marshall, Bryan, Chen, Tilden, Triano, Alex, Nayak, Bibhu, Muniganti, Harikiran, Sivaswamy, Joe, Gope, Dipanjan
Format: Conference Proceeding
Language:English
Published: IEEE 15-10-2023
Subjects:
Correlation
Electromagnetic compatibility
Integrated circuit modeling
Predictive models
Silicon
Solid modeling
Switches
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Summary:Isolator integrated circuits (ICs) that employ AC switching to send power or data across magnetic or capacitive insulation barriers can create excessive transient di/dt and dv/dt loops that exacerbate electromagnetic emissions. In this work, we developed a robust system-level coupled circuit-to-electromagnetic modeling and analysis methodology to predict the CISPR 25 conducted emission performance of an automotive isolated solid-state relay during product development. The coupled method accurately captures the electromagnetic interactions between the nonlinear time-variant power switchers and the system. Preliminary silicon validation measurements on an automotive isolated solid-state relay are presented to validate the integrity of the predictive modeling methodology. In an EMC pre-compliance lab, good correlations between modeling and measurements are achieved (i.e., within +/- 2-5dB) for emission peaks within the frequency band of 0.15MHz-108MHz. The predictive EMC modeling methodology can be implemented to assess the performance of the initial silicon design during early IC development.
ISSN:2165-4115
DOI:10.1109/EPEPS58208.2023.10314874