Search Results - "Chatha, Karam S."

Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors by Hanumaiah, V., Vrudhula, S., Chatha, K. S.

“…Extracting high performance from multi-core processors requires increased use of thermal management techniques. In contrast to offline thermal management…”
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Linear-programming-based techniques for synthesis of network-on-chip architectures by Srinivasan, K., Chatha, K.S., Konjevod, G.

“…Application-specific system-on-chip (SoC) design offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for…”
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Guest Editors' Introduction - Special Issue on Network-on-Chip by Ginosar, Ran, Chatha, Karam S.

“…Network-on-Chip (NoC) has emerged as a key architecture component that determines the overall performance, power, and area (PPA) of a contemporary…”
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Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique by Leary, G., Srinivasan, K., Mehta, K., Chatha, K.S.

“…The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the…”
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An Embedded Architecture for Energy-Efficient Stream Computing by Panda, Amrit, Chatha, Karam S.

“…Stream processing has emerged as an important model of computation in the context of multimedia and communication subsystems of embedded system-on-chip (SoC)…”
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Thermal aware task sequencing on embedded processors by Sushu Zhang, Chatha, Karam S

“…We seek to maximize the throughput of a periodic application by obtaining an optimized task sequence and dynamic voltage/frequency scaling schedules subject to…”
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Hardware-software partitioning and pipelined scheduling of transformative applications by Chatha, K.S., Vemuri, R.

“…Transformative applications are computation intensive applications characterized by iterative dataflow behavior. Typical examples are image processing…”
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Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints by Srinivasan, Krishnan, Chatha, Karam S.

“…The increased complexity and performance requirements of embedded systems has led to the advent of programmable multiprocessor architectures. The paper…”
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Quality-of-service and error control techniques for mesh-based network-on-chip architectures by Vellanki, Praveen, Banerjee, Nilanjan, Chatha, Karam S.

“…Network-on-a-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance system-on-chip architectures in the…”
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Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules by Sushu Zhang, Chatha, K S, Konjevod, G

“…We address power minimization of earliest deadline first and rate monotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard,…”
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Linear programming based techniques for synthesis of network-on-chip architectures by Srinivasan, K., Chatha, K.S., Konjevod, G.

“…Network-on-chip (NoC) has been proposed as a solution for the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design…”
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Approximation algorithm for data mapping on block multi-threaded network processor architectures by Ostler, Chris, Chatha, Karam S.

“…Network processor architectures incorporate block multi-threading to alleviate the performance degradation due to memory access latencies. Application design…”
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Iterative algorithm for hardware-software partitioning, hardware design space exploration and scheduling by Chatha, Karam S, Vemuri, Ranga

“…The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique…”
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Unrolling and retiming of stream applications onto embedded multicore processors by Che, Weijia, Chatha, Karam S.

“…In recent years, we have observed the prevalence of stream applications in many embedded domains. Stream applications distinguish themselves from traditional…”
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Layout aware design of mesh based NoC architectures by Srinivasan, Krishnan, Chatha, Karam S.

“…Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces…”
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Performance and resource optimization of NoC router architecture for master and slave IP cores by Leary, Glenn, Mehta, Krishna, Chatha, Karam S.

“…System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper…”
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Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures by Chatha, K.S., Srinivasan, K., Konjevod, G.

“…This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements…”
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A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures by Srinivasan, K., Chatha, K.S.

“…Network-on-chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale…”
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Smart driver for power reduction in next generation bistable electrophoretic display technology by Baker, Michael A., Shrivastava, Aviral, Chatha, Karam S.

“…Microencapsulated electrophoretic displays (EPDs) are quickly emerging as an important technology for use in battery-powered portable computing devices. Thanks…”
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A technique for low energy mapping and routing in network-on-chip architectures by Srinivasan, Krishnan, Chatha, Karam S.

“…Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC…”
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